搜索资源列表
VHDLDPLL
- 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
DPLL_verilog
- 一阶全数字锁相环VERLOGIC程序代码，调试通过。
adpll
- 全数字锁相环 功能与74297相同 提供参数配置
ADPLL.rar
- 全数字锁相环（adpll)的部分源程序代码，是其中最重要的部分。,All-digital phase-locked loop (adpll) part of the source code, is one of the most important part.
FPGA-based-design-of-DPLL
- 采用VHDL设计的全数字锁相环电路设计，步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
DPLL2
- 全数字锁相环电路的研制，使用的是VHDL语言 -All-digital phase-locked loop circuit development, using the VHDL language
FPGA444555443
- 基于FPGA的全数字锁相环设计,内有设计过程和设计思想-FPGA-based all-digital phase-locked loop design, with the design process and design thinking
pll_verilog
- 全数字锁相环的verilog源代码,仿真已通过 -All-Digital Phase-Locked Loop verilog source code, simulation has passed
pll_code
- 全数字锁相环的verilog源代码-全数字锁相环的verilog源代码
VHDLDPLL
- 基于VHDL 的全数字锁相环的设计，里面包含了最核心的程序。-VHDL-based all-digital phase-locked loop design, which contains the core procedures.
DPLL
- 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
DPLL_verilog_a
- 用verilog语言描写设计的全数字锁相环，pDF资料-With the verilog language to describe the design of all-digital phase-locked loop, pDF information
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
vhdl3
- 介绍一种基于VHDL 语言的全数字锁相环实现方法， 并用这种方法在FPGA 中实现了全 数字锁相环，作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demodulation of bit synchronizatio
VHDL-FPGA-ALL-digital-DDLL
- VHDL 全数字锁相环 ise7.1i环境实现 内有代码 和时域仿真结果-A VHDL language based on all digital phase-locked loop DPLL VHDL realization
a-adpll-based-on-fpga
- FPGA实现的VHDL语言的全数字锁相环-a adpll based on fpga
FdplllzipP
- ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
verilog_PLL
- 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simula
dpll
- 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)