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4bit数据的加减乘除
- 一个很不错的例子,实现的是4bit的加减乘除,用modelsim做的仿真.-a very good example of the realization of the Band is the arithmetic, modelsim do with the simulation.
alu64_struct
- 六十四位ALU设计源代码，可实现加减，逻辑与，或等多种功能。-64 ALU design source code can be modified to achieve, and logic, or other functions.
4bits_alu
- 实现4位加减乘除的alu，采用超前进位加法和布斯乘法，代码较为简单。-achieve four of the ALU arithmetic using CLA Bush and multiplication, code more simple.
bmpelipse
- 实现矩阵的各种操作，加减乘，下载该类可放面以后的编程。-achieve the matrix operation, modified by downloading such caving face future programming.
Ivga
- 用VHDL写的计算器，实现加减功能以及ＶＧＡ显示功能，适合VHDL初学者使用。-VHDL write calculators, Modified functions and achieve VGA display, VHDL for beginners.
add_sub_lab2
- 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl descr iption, including analysis and reporting.
keyboard__1.1
- 实现数码管输入显示器输出功能（加减乘除运算）-realization of the digital input output function display (arithmetic operations)
calculation2
- 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0 -- 100 within a simple calculator function in the source code. including the four arithmetic operations function
foudiv
- 可以实现对任意波形分任意频，分频加减通过按键实现。
calculator
- 用VHDL编写的计算器，能实现简单的加减乘除四则运算
updowncnt
- 加减计数器，其实也没什么，想要就拿去了，给我拿别人的东西才重要
as.rar
- 自己编写的的，基于verilog的加减法器！！！比较简单！！,Their written, based on instruments used in verilog addition and subtraction! ! ! Is relatively simple! !
vhdl_123
- 几个简单的vhdl程序。包括加法器，减法器，乘除法等等。-A few simple vhdl program. Including the adder, subtractor, multiplication and division and so on.
VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
calculator
- VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出-Calculator written with VHDL
cpu2
- 另一个简单的16位VHDL的CPU程序~~~包含简单的加减乘除移位等操作，适用于课程设计-Another simple VHDL' s CPU 16-bit program ~ ~ ~ contains simple calculation shift and other operations for course design
OPERATION_UNIT
- 本程序为加密芯片内部加密运算单元部分，包括32位减法器、移位寄存器、加/减法器、寄存器等，对密码芯片运算部分设计具有一定指导意义-The procedure for encryption chip unit internal encryption algorithms, including 32-bit subtraction, and shift register, add/subtraction, and register and so on password-chip design has
bhgfdti
- 含有七人表决器，格雷码变换电路，英文字符显示电路，基本触发器（D和JK），74LS160计数器功能模块，步长可变的加减计数器-Containing seven people vote, and Gray code conversion circuit, the English characters display circuit, the basic flip-flop (D and JK), 74LS160 counter function modules, variable-step add
jiajianfaqi
- 利用VHDL语言设计的两位加减法器，设计采用BLOCK并行设计可以同时进行加法与减法运算-VHDL language design using addition and subtraction of two instruments used, designed using BLOCK parallel design can be done concurrently addition and subtraction
ADD_SUB_32bit
- 加减法器，可实现有无符号数的加减法-Modified instruments used, can be realized whether the number of addition and subtraction symbols