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cnt10
- vhdl 十进制加法计数器设计 已经调试成功-decimal adder vhdl counter the success of design debugging
pinlvji
- 频率计VHDL编程。设计一个4位数字显示的十进制频率计，其测量范围为1MHz，测量值通过4个数码管显示以8421BCD码形式输出，可通过开关实现量程控制，量程分10kHz、100kHz、1MHz三档(最大读数分别为9.999kHz、99.99kHz、999.9kHz)； 当输入信号的频率大于相应量程时，有溢出显示。 -Cymometer VHDL programming. Design of a 4-digit decimal display frequency, the measure
paobiao
- 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
juzhenjianpan
- 本源码用VHDL语言实现了用键盘控制米字管显示十进制-VHDL
eight_decimal
- 用VERILOG写的8位十进制频率计 注释非常清晰 有助菜鸟学习-VERILOG written with eight decimal Notes Cymometer help rookie learning very clear
count10
- 基于Quartus II的十进制加法计数器的项目设计，包含了项目文件和VHDL源代码-Quartus II based on the decimal adder counter the project design, including project documents and VHDL source code
cd4000x
- CD4000 双3输入端或非门+单非门 TI CD4001 四2输入端或非门 HIT/NSC/TI/GOL 双4输入端或非门 NSC CD4006 18位串入/串出移位寄存器 NSC CD4007 双互补对加反相器 NSC CD4008 4位超前进位全加器 NSC CD4009 六反相缓冲/变换器 NSC CD4010 六同相缓冲/变换器 NSC CD4011 四2输入端与非门 HIT/TI CD4012 双4输入端与非门
Cymometer_of_four_decimal
- 四位十进制数字频率计： 测量范围：1Hz～10kHz； 显示时间不少于1S； 具有记忆显示的功能，即在测量过程中 刷新数据，等结束后才显示测量结果，给出待测信号的频率值，并保存到下一次测量结束。-Four decimal digital frequency meter: measuring range: 1Hz ~ 10kHz show that no less than 1S with memory function showed that the cour
counter
- 这是用VHDL设计的十进制计数器，两个VHDL程序分别说明了out和buffer的区别-It is designed with VHDL decimal counter, the two VHDL procedures were illustrated the difference between out and buffer
vaa
- （１）设计一个4位十进制的频率计其测量范围1Hz~9.999KHz；6 N3 G8 k( U- @ n* A （２）记数过程结束后，保存并显示结果；-(1) to design a metric four of its frequency range 1Hz ~ 9.999KHz 6 N3 G8 k (U-@ ' n* A (2) After the counting process, preserve and display the results
jishuqi8421
- 用VHDL语言实现8421码的十进制计数器，状态变化0000->0001->0010->0011->0100->0101->0110->0111->1000->0000.循环往复。 -VHDL language with 8421 yards of the decimal counter, a state of change 0000-> 0001-> 0010-> 0011-> 0100-> 0101-&g
shijinzhi
- 利用FPGA做出十进制加减法！带有进位借位显示-FPGA to make use of the decimal addition and subtraction! By a binary digital display
Quartus32
- 1.8421码十进制计数器 2.分频系数为8，占空比为0.5的分频器 3.控制8个二极管的电路-Counter 2 decimal 1.8421 yards. Sub-frequency coefficient of 8, duty cycle of the divider 3 for the 0.5. 8 diode control circuit
seven_segment
- 用veirlog写成的七段显示器 可以把十进制转成七段显示器上面的显示数字-Paragraph written by veirlog display can display the metric system into the above paragraph shows that the number of
dig_scan
- 将AD采样的八位比特转化为十进制数值大小，并用数码管动态显示-The AD sample into the eight-bit decimal numerical size, and dynamic display with digital control
counter1
- 带复位和时钟使能的十进制计数器 verilo 描述-With reset and clock enable verilo descr iption of the decimal counter
counter
- 利用EDA工具MAX-PlusII的VDHL输入法，输入VHDL程序，实现2位计数器，在七段译码器上以十进制显示：0、1、2、3、0、...。时钟信号使用83管脚。采用自动机状态转换方式设计该计数器；建立相应仿真波形文件，并进行波形仿真；分析设计电路的正确性。-The use of EDA tools VDHL of the MAX-PlusII input method, enter the VHDL program, the realization of two counters, in t
38-decoder
- 38译码器，和一般的38译码器一样，二进制与十进制的对应-Decoder 38 and decoder 38 in general, as the corresponding binary and decimal
miaobiao
- VHDL语言实现秒表并在共阴数码管上动态显示十进制数值-VHDL language stopwatch and digital control on a total of negative dynamic display decimal values
EDA
- EDA实验讲义GK 包含GW48 EDA系统使用说明以及许多实例。比如有时钟使能的两位十进制计数器原理图输入设计、用状态机对ADC0809的采样控制电路实现、硬件电子琴电路设计-EDA experimental GK notes GW48 EDA system contains, as well as many examples of use. For example, there are two clock-enabled input decimal counter schematic des