压缩文件内含有VHDL和VERILOG编写的SDRM控制源码，已通过编译，均可直接使用。-Zip file contains VHDL and VERILOG source code written in SDRM control, has passed the compilation, can be used directly.

该压缩文件是基于FPGA的SOPC系统基本测试程序-The zip file is the basic FPGA-based SOPC system test procedures

实现跨时钟域数据传输的异步fifo，和i2c总线控制器。(Asynchronous FIFO and I2C bus controller for cross clock domain data transmission.)