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ddc_virtex5
- 数字光纤直放站上使用的V5一级变频系统，是其基带板的核心-V5-level inverter system used on the digital fiber optic repeater
3-ddc-cic_5hb_firmatlab-testbench)
- 三通道上下变频cic_5hb_firmatlab仿真程序-Three-channel down conversion cic hb fir matlab simulation program
CIC_filter
- 抽取:(接收端) 中频信号IF 20M(采样率是50M) 下变频信号 MIX_O 1M(50M) 采用CIC滤波器进行降采样率。 插值:(发送端) 基带信号上变频到1M，采样率是2.5M，采用CIC滤波器进行升采样率处理。 注释：升采样率或者降采样率不会改变原始信号的中心频率，但是频谱分布会发生改变。-Extraction: (receiver) IF signal 20M (sampling rate is 50M) down-conversion signal M
cic10_sec5
- 抽取因子可调，四级梳状滤波器，在数字下变频中会使用到(The decimation factor is adjustable, and the four stage comb filter is used in digital down conversion)
DDC中的抽取滤波器设计及FPGA实现
- 本文对下变频模块中抽取滤波进行了详细的分析，并详细阐述了其FPGA的实现过程和方法(In this paper, the decimation filtering in the down conversion module is analyzed in detail, and the realization process and method of FPGA are discussed in detail)
oo
- 利用xilinx公司开发的vivado平台，实现下变频功能(We use the vivado platform developed by Xilinx to realize the down conversion function.)
one_1bit
- 利用xilinx公司开发的vivado平台，实现调用1bitpwm信号实现下变频的功能(Using the vivado platform developed by Xilinx, we can realize the function of calling down the 1bitpwm signal to realize the down conversion.)
ddc
- 下变频采样、本振和滤波三个过程涉及到的详细代码与注释(Detailed code and notes for down conversion sampling, local oscillator and filtering)
down_up_dds
- 在Vivado下完成AD输入到下变频的功能，频率可配置，通用化设计。(The function of AD input to down conversion is completed under Vivado, and the frequency is configurable and universal design.)