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5bit-adder-subtracter
- 5 bits 的加法器與減法器合併電路之原始程式製作
combine_module
- 本代码根据包头、包尾指示，将两路数据合路调度成一路输出
fujie_78
- 利用Quartus ii实现的两路数据按位复分接，使用Verilog语言编程。两路数据码率都同为78Kb/s,复接后的合路速率为156Kb/s,加帧头后的速率变为160Kb/s.分接端为上述流程的逆过程。-Implemented using Quartus ii two-bit multiplexed data by tapping, using Verilog language programming. Two-way data rate are the same as 78Kb/s, aft
ALU-and-Register-File
- ALU&Register Files(RF)之實現和其資料路徑的組合，包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.
debun1
- 使用D型正反器,使開關防彈跳電路,規劃一個模組電路,也可組合多個模組,來配合多個開關輸入-D-type flip-flop, the switch anti-bounce circuit, planning a modular circuit can also be a combination of multiple modules to fit more than one switch input
sw_bit8_latch
- 組合8個開關防彈跳,再加栓鎖電路,可讓開關動作更穩定-A combination of eight key anti-bounce, plus latch circuit allows the switching action is more stable