一个数字电子钟的设计，有VHDL并含电路图-A digital electronic clock design of the VHDL and the circuit containing

verilog hdl实现多周期CPU，按照有限状态己设计，含源码、实验报告和详细vsd电路图-verilog hdl multi-cycle CPU, in accordance with the finite-state has been the design, including source code, test reports and detailed schematic vsd

主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动，SRAM型号为IS61LV25616，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图-Mainly based on FPGA (EP2C8Q208I8) driving under the SRAM, SRAM model IS61LV25616, programming language for Verilog, a development environment for

主要是基于FPGA(EP2C8Q208I8)下的高速AD9215驱动，程序语言为Verilog,开发环境为quartusII 7.0,为一工程，可直接下载到FPGA中，含电路图-Mainly based on the high-speed AD9215 FPGA (EP2C8Q208I8) under the driver, the programming language for Verilog, a development environment for quartusII 7.0, for