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mul
- 在gf(2^13)中,固定因子乘法器(基于自然基,0-128)
IS-95/CDMA2000基带成形滤波器的实现
- IS-95/CDMA2000基带成形滤波器的实现 IS-95滤波器的实现: 本次设计采用转置型结构,并用展开技术将字串行架构转换成字并行处理架构,从而提高运行的速度。本次设计中采用展开因子J=4的展开转换技术。设输入数据为filter_in,输出数据为filter_out,则其展开因子J=4的并行处理系统如下图所示 ,IS-95/CDMA2000 base-band filter shaping to achieve IS-95 filter to achieve: the desig
FFTbutter
- FFT的旋转因子算法和蝶形处理器VHDL代码实现-The rotation factor FFT butterfly processor algorithm and VHDL code
fft
- 基于VHDL语言编写的FFT程序,256点,旋转因子存在自己编写的ROM里面,乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
FFT
- 2点的碟形算法,其中包含了旋转因子乘法器,这是一种高效的复数乘法器.-2point dish method, which includes the rotation factor multiplier, which is a highly efficient complex multipliers.
ccmul
- FFT旋转因子,旋转因子是蝶形运算的组成部分,是数字信号处理FFT算法的基础部分-FFT twiddle factor, rotation factor is an integral part of the butterfly, digital signal processing is a fundamental part of FFT algorithm
SPA
- 首先介绍了LDPC码的校验矩阵和其因子表示方法,然后利用二分图对和积解码算法进行了详细的描述,最后给出了信度传播概率译码算法详细步骤,并对关键公式作了证明-This paper,first introduces the check matrix and the factor graph of LDPC,then describes the sum-product algorithm by using the factor graph,and finally presents the deta
bfly_r2dit
- 这是一个用verilog编写的FFT的蝶形因子程序,它与下面的文件构成整个FFT程序-This is a written with verilog program FFT butterfly factor, file it with the following procedures constitute the whole FFT
ccmul
- FFT中 旋转因子8位复数乘法的VHDL程序,3次实数乘法和3次加减法运算,-FFT twiddle factor of the VHDL program, 3 times real multiplication and subtraction 3
butterfly1
- FFT 蝶形处理器的VHDL代码,由一个加法器,一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul
eetop.cn_fft
- 采用全流水线结构,供初学者参考,附有仿真波形图,代码中上有可以改进之处,如蝶形单元中可以将4次乘法简化为3次乘法,不过要预先对旋转因子做处理,第一次上传,如有不妥之处,还请大家指正,谢谢。 -With full pipeline structure, reference for beginners, with a simulation waveform diagram, the code can be on improvements, such as the butterfly unit
video_stream_scaler
- 该模块能对视频分辨实时缩放,采用最近邻域和双线性差值算法。该模块可以实时配置输入输出的分辨率、缩放因子,缩放算法类型等参数,也可在编译时采用默认配置。-The Video Stream Scaler (streamScaler) performs resizing of video streams in a low latency manner, resizing with either bilinear or nearest-neighbor modes.The core offers run
1024-FFT-VHDL
- 1024点FFT的VHDL程序,含碟形图,旋转因子存储及产生代码,最后是VHDL整体设计,quartus ii编译环境-1024-point FFT VHDL program, including dish-shaped figure, twiddle factor , last VHDL overall design, Quartus ii compile environment
fft
- 实现功能:基8实现64点FFT处理器(进行两次8点FFT计算,采用基8进行64点) 详细说明:硬件结构包括六部分,分别为输入模块、8点FFT模块、乘法模块、顺序调整模块、输出模块和总控制模块。 其中,输入模块的主要功能是将串行输入的64个数据进行分类,分成8批次,每次8个输入到8点FFT模块中进行计算。 8点FFT模块:FFT是DFT的快速算法,当点数较大时,可以较大的减少DFT的运算量。常用的FFT算法主要有两种,分别为按时间抽选的FFT算法(DIT-FFT)和按频率抽选的FFT算
cic10_sec5
- 抽取因子可调,四级梳状滤波器,在数字下变频中会使用到(The decimation factor is adjustable, and the four stage comb filter is used in digital down conversion)