搜索资源列表
sdram_ctrl1.rar
- FPGA读写SDRAM的VHDL程序，已经测试过,FPGA to read and write the VHDL procedures SDRAM have been tested
sdramcontroller.rar
- FPGA读写SDRAM的VHDL程序(已经测试过),SDRAM read and write the VHDL program FPGA (already tested)
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
ICX408AL7.5M
- 基于CPLD的CCD驱动程序源码，本人已经测试过，配合单片机控制，就能实现CPLD对CCD的驱动控制和曝光控制-CPLD based on the CCD driver source, I have been tested with single-chip control, you can achieve CPLD driver for CCD control and exposure control
VHDL312vh6
- 包含若干个VHDL小例子，有交通灯，电子琴，简易秒表，等等，交通灯已经测试过，根据自己的需要，稍微改动，很好用！-VHDL contains a number of small example, there is traffic lights, Electronic organ, simple stopwatch, and so on, traffic lights have been tested, according to their own needs, slightly altered,
i2c_AT2402
- 用VHDL语言编写的AT24C02程序，并用数码管显示，本程序已经经过本人测试过，很好用-The AT24C02 is available VHDL language program, and use digital tube display, this procedure has been tested himself, very good to use--
fira
- 这是一个用FPGA中DSP Bulider做的一个FIR滤波器，很好使用，我已经测试过了-This is an FPGA, DSP Bulider used to do a FIR filter, a very good use, I have tested the
a12
- FPGA读写SDRAM的VHDL程序(已经测试过)-FPGA SDRAM read and write the VHDL program (already tested)
cf5_0
- 标准niosii，具有CF接口，可以读写CF卡，已经测试过可以使用-Standard niosii, a CF interface, CF card can read and write, has been tested using
EDA
- 程序是用verilog HDL语言写成的抢答器，已经进过测试，绝对可以运行-Program is written in verilog HDL Responder, has been to test, absolutely you can run
mysopc
- 基于友晶DE0开发板做的NiosII最小系统，主要是修正了开发板上闪存连线错误，已经测试过，烧到DE0里面就直接可以跑了。SDRAM和FLASH存储器都可以正常运行，里面还有一个用于点亮LED的小程序，是用软核实现的，从而证明该最小系统可以正常运行，其余的扩展可以自行开发-Friends of grain-based development board to do NiosII DE0 minimum system, mainly Fixed connection error on the de
PWM
- PWM控制技術，已经测试过，可以放心下载应用！-PWM control techniques, have been tested, you can rest assured that download the application!
cordic
- cordic的实现代码，我已经测试过了，很好用的-cordic implementation of the code, I have tested, and very easy to use
uart-vhdl
- 不错的uart总线程序，已经测试过，没有问题啊-Good uart bus program, has been tested, there is no problem ah
graph
- max+plus2 入门的模为12的计数器，测试过已经通过。-verilogHDL 12_counter
CHENGXU
- 程序实现的功能是在一个8*8的数码管上实现汉字滚动实验。程序已经测试过了。-Realize the function is in an 8* 8 digital tube experiments to achieve Chinese scroll. Program has been tested.
PtDdcCic3
- CIC三级抽取滤波器源代码，包括modelsim的仿真代码，已经测试过稳定性-cic 3 cascade filter source code， including modelsim simulation code， and test
uart(Verilog)
- uart 测试源码，已经测试过，非常好用-uart test code
float_2_int.v
- 最全的，最简单，32位浮点数转整数，32位整数转浮点数，直接可以移植，已经测试过好用。(The most complete, the simplest, 32 bit floating-point integer, 32 integer floating point number, can be directly transplanted, has been tested, easy to use.)