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fpga.fifo
- 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the
rs232
- 异步串行传输的verilog hdl 功能文件以及测试文件-The verilog hdl source and the testbench of asynchronous serial transmission
UART
- UART是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中，UART用来与PC进行通信，包括与监控调试器和其它器件，如EEPROM通信。-UART is a universal serial data bus for asynchronous communication. The two-way communication bus, can achieve full-duplex transmit and receive. In embedded d
AVD
- 现代的IC芯片包含丰富的触发器，不同电路的时钟驱动源存在频率和相位的差异，因而出现了跨不同时钟区域进行异步数据传输的要求。亚稳态问题是异步数据传输过程面临的主要问题，本文提出多种跨越异步时钟边界传输数据的方法，它们包括FIFO法和脉冲展宽处理等同步方法。 -Modern IC chip contains a wealth of trigger, the clock drive source different circuit exists between the frequency and ph
uart_16550
- UART是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中，UART用来与PC进行通信，包括与监控调试器和其它器件，如EEPROM通信。-A UART that is compatible with the industry standard 16550D includes wrappers for the Wishbone and AMBA APB busses
uart
- 串行异步收发接口，简称UART，是一种广泛应用的串行传输接口。这是用vhdl实现的程序，将UART分成相应的几个模块，并用顶层文件进行模块化设计。-Send and receive asynchronous serial interface, referred to as the UART, is a widely used serial transmission interface. This is achieved using vhdl procedure to the appropriat
fifo
- 异步FIFO是一种先进先出的电路，使用在需要产时数据接口的部分，用来存储、缓冲在两个异步时钟之间的数据传输。- Asynchronous FIFO is the electric circuit which one kind advanced leaves first, uses when needs to produce data interface s part, uses for to save, the cushion between two asynchronous clock s d
yibufifo
- 基于verilog的异步驱动电路的设计传输实现与研究详解-Verilog-based asynchronous driver circuit design to achieve transfer and research Detailed
asynchronous-clock-boundary
- 一个关于跨越异步时钟边界传输数据的解决方案-The solution of transfering data across asynchronous clock boundary.
68013A_BULK_TRANS
- CY68013A异步BULK传输范例，严格按照时序描述来进行读写，对fifo实现读写，功能完善。-CY68013A asynchronous BULK transmission model, in strict accordance with the temporal descr iption to read and write, read and write to the FIFO implementation, perfect function.
rs232
- 异步传输标准接口rs232的fpga程序，非常好用-very useful
uart_rx
- uart通信方式的接受模块，在串口通信uart中，需要记录来自外设的数据，进行采集和时序控制，进行异步的传输。-acceptance uart communication module, serial communication uart need to record data from peripherals, acquisition and timing control, asynchronous transmission.
uartfifo
- 同步异步传输协议的应用通过调试助手向FPGA发送数据，然后再读出来，-Application of synchronous and asynchronous transmission protocol to send data to the FPGA debugging assistant, and then read out
uartfifo
- FPGA采用FIFO实现UART，对于大量异步数据的采集传输很有帮助-A usart design of FPGA using fifo,it can be used in massed asychronous data collect.
FPGA-FIFO
- FPGA-跨时钟域总线信号可靠传输异步FIFO技术安全可靠，格雷码计数，减少亚稳态-FPGA-clock domain crossing bus signals reliable transmission of asynchronous FIFO safe and reliable, Gray code count, reducing the metastable
baud_gen
- Uart是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中。其中本代码为UART的波特率产生代码。-Uart is a universal serial data bus, used for asynchronous communication. The bus bidirectional communication, can realize the full duplex transmission and reception. In embedded
rom
- uart 通用异步收发传输器 接收模块和发送模块 附带了常用的波形 三角波 和正弦波-uart universal asynchronous receiver transmitter receiver module and transmitter modules come with a common triangular wave and sine wave
rx_uart
- rx_uart。uart是通用异步收发传输器，是电脑硬件的一部分。-rx_uart.uart is a universal asynchronous receiver transmitter, is part of the computer hardware.
ASI
- 异步串行接口ASI,QUARTUS cv demo参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI, QUARTUS cv demo reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
新建 WinRAR ZIP 压缩文件
- 实现跨时钟域数据传输的异步fifo，和i2c总线控制器。(Asynchronous FIFO and I2C bus controller for cross clock domain data transmission.)