搜索资源列表
CPU2
- 利用VHDL编写的简单CPU程序，能进行简单的加减运算，有运算结果截图的
VHDLexample
- VHDL开发程序，有程序仿真的截图，方便验证调试结果。并有程序说明
verilog_code
- 有用的verilog hdl实验用程序 配有截图
SPI_AT45DB041B.rar
- 用verilog编写的SPI程序,SPI芯片是AT45DB041B.文件内包含程序仿真时的截图.包括read和wirte.,SPI prepared using Verilog procedures, SPI chip AT45DB041B. Document contains procedures for simulation screenshot. Including read and wirte.
CMI
- 基于FPGA/CPLD的CMI编解码设计，含程序说明及仿真截图。-Based on FPGA/CPLD' s CMI codec design, including descr iption of the procedures and simulation screenshot.
Cordic_SinCos_Verilog
- 用Verilog语言写的Cordic来计算，正、余弦函数，包括仿真激励和仿真截图。-use Cordic to compute sine and cosine function
decoder_2_10
- 采用VHDL语言编写的二-十进制编码器，在MAX+plus软件上实现，其中包括演示截图。-Using VHDL languages II- Decimal encoder, in MAX+ Plus software to achieve, including the demo screenshot.
Quartus7.2andModelSim
- 结合截图，quartus2与ModelSim的联调的详细操作步凑，使初学者迅速上手-Combination of shots, quartus2 with the ModelSim FBI put together a detailed step-by-step operation, so that beginners get started quickly
traffic
- verilog编写的一个交通灯程序，利用状态机实现。压缩包内有说明文档，源代码及时序截图-verilog prepared a program of traffic lights, the use of state machine to achieve. Compressed packet, there are documentation, source code and timing Screenshots
Digitalfrequency
- 数字频率计VHDL程序与仿真,附有仿真截图和源程序注释-Digital frequency meter VHDL procedures and simulation, with simulation screenshots and source code comments
CPUdesign
- 计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。-Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.
8255compile
- 对8255的三个I/O接口进行单个运行并仿真，测试准确可用，并进行了截图。-Three of the 8255 I/O interface to a single run and simulation, test accuracy available, and were shot.
ISE_instruction
- ISE 9.1的使用指南，有详细的使用方法和截图描述-ISE instruction
ISE-anzhuangjiaocheng
- ISE安装详细说明，包括工程开发流程，测试文件编辑等，包括大量截图，非常适合初学着。-ISE installation details, including engineering processes, testing, editing documents, including a large number of shots, is very suitable for beginners with.
VHDLshixianCPU2
- vhdl实现cpu用verilog写的8位CPU源码，通过汇编语言可以实现加减乘左移右移等运算。并通过ASC流程可以模拟出其内部电路结构。代码，截图，readme在文件夹中-With 8-bit CPU to write verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. ASC process throu
CORDIC_SinCos_VHDL
- 用 VHDL 语言写的 Cordic模块，来计算正、余弦函数，包括仿真激励和仿真截图。-use Cordic to compute sine and cosine fuction in VHDL
hdb3verilog
- 实现基于verilog语言的HDB3的编玛功能 有截图和代码解释 -HDB3 encoding
55593402DDS_vhdl
- DDS分频实现，全部代码的完整过程，包括截图等-DDS divider to achieve the complete process of all the code
3-8-decoder
- 三八译码器,用Verilog HDL语言描述，包含文件说明以及波形截图-3-8 decoder using Verilog HDL language descr iption, including documentation and waveform capture
8-1-mux
- 八选一数据选择器，Verilog HDL语言描述，包含文件说明和波形截图-8-1 MUX, Verilog HDL language descr iption ， contains the file descr iption and waveform capture