搜索资源列表
parallel-output-controller-(POC)
- 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
QuartusII-plj
- 用QuartusII与FPGA设计等精度频率计，内附程序、设计思路、设计报告，内容翔实，功能强大-QuartusII and FPGA design using precision frequency meter, containing procedures, design ideas, design reports, informative and powerful
mooreb
- EDA实验状态机经典程序及图形仿真文件和实验报告,对实验参考绝对有益处-classical procedures and graphical simulation and experimental paper that reports on the experiment are likely to benefit from the absolute reference.
DDS
- 内含DDSFPGA程序和51单片机控制程序和报告一份-Containing DDSFPGA procedures and 51 procedures and reporting a single-chip control
design
- 计算机组成原理课程设计报告 微程序控制计算机设计-Principles of Computer Organization course design report Micro-program control computer design
jing
- 用VHDL语言编程一个具有秒计时，定时的数字时钟，其中包括程序，图示，仿真结果及报告。-VHDL programming a stopwatch, digital clock timing, including procedures, icon, simulation results and reports.
Design-of-traffic-lights
- 针对十字路口交通信号灯的设计。开发工具为Quartus II 5.1。内含完整报告和可运行程序文件。功能非常好，可做学习参考。-For the design of the traffic lights at the crossroads. Development tools for the Quartus II 5.1. Containing the full report and run the program file. Very good, to do with learning refe
Automatic-pencil-sharpener
- 针对自动售铅笔机的数字逻辑设计，开发工具为Quartus II 5.1。内含完整报告和可运行程序文件。可做学习参考，于君共勉。-Pencil vending machine of digital logic design, development tools for the Quartus II 5.1. Containing the full report and run the program file. Do as a reference in the king of mutual enc
Digital-competition-responder
- 数字式竞赛抢答器的VHDL程序及实验报告，本抢答器是最多可容纳5位参赛者的数字式抢答器，在QUARTUS II平台中进行了仿真-VHDL procedures and lab reports Digital contest Responder, the Responder is for up to five contestants digital Responder, a simulation platform in QUARTUS II
FULL_ADD
- 编写一位全加器的程序，生成器件后用BLOCK画出bdf图，最终成为四位全加器。此为实验报告，里面包括原理及框图及源程序。-Preparation of a full adder program, after generating device using BLOCK draw bdf map, eventually become four full adders. This is a test report, which includes the principle and block diag
bubblesort
- 根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果，含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)