搜索资源列表
VHDL
- 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码
moore_in_and_mealy_out_state_machine
- 此程序为带摩尔输入、米勒输出状态的状态机控制部分-This procedure with Moore for input, Miller output state control of some of the state machine
state_machine_design
- 这是讲解状态机的一个资料，里面讲解了摩尔和米勒状态机的设计实例，很详细且有实例。-This is a state machine on the information, which Moore and Miller explained the design of state machine instances, and there are examples of very detailed.
state_machine
- 摩尔状态机的程序，超经典的，用VHDL写的，初学者可以参考-Moore state machine program, ultra classic, written with VHDL, beginners can refer to
moore
- 摩尔有限状态机的例子很好的，实验读写控制-an example of FSM of moore
fsm_moore_1_always
- 使用1个always块描述Moore FSM（摩尔状态机）-Moore FSM 1 always
ztj
- 摩尔状态机检验程序，序列检测器，1100101检测-Moore state machine testing procedures, the sequence detector, 1100101 test
State_Machine
- 状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state
moore-FSM
- 该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用-The program describes the simulation and the function and role of a mole finite state machine
sos_module
- 用FPGA实现sos摩尔密码，即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。而 control_module.v 是一个简单的定时触发器，每一段时间都会使能sos_module.v。-Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password,
状态机
- 米利机和摩尔机的vhdl基本代码，可以自己更改
1
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio
2
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 l