搜索资源列表
dcm
- Xilinx的V4FPGA数字时钟管理模块的底层原语实现代码，硬件上跑通- The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
a_digital_time_keeper1
- 数字时钟 已经在quartus2仿真验证过 VHDL代码-Digital clocks already in quartus2 simulation validated VHDL code
clk_div8
- 基于vhdl语言的源代码，主要用于八位的数字时钟进行操作，会用到进位-Vhdl source code based on the language, mainly for the eight digital clock operation, will use the carry
szshizhong
- VHDL语言实现数字时钟，并可以显示时和秒-VHDL, digital clock, and can be displayed and the second
multifunction-digital-clock
- EDA课程设计多功能数字时钟的设计程序源码，在Cyclone II上验证成功！-EDA curriculum design process multifunction digital clock source, the Cyclone II verify success!
digital-clock
- 数字钟是计时仪器，它的功能大家都很熟悉。本实验对设计的电子钟要求为： 1．能够对s(秒)、min(分)和h(小时)进行计时，每日按24h计时制； 2．min和h位能够调整； 3．设计要求使用自顶向下的设计方法。 数字钟的功能实际上是对s信号计数。实验板上可提供2Hz的时钟，二分频后可产生s时钟。数字钟结构上可分为两个部分c计数器和显示器。计数器又可分为s计数器、min计数器和h计数器。s计数器和min计数器由6进制和10进制计数器构成，小时计数器较复杂，需要设计一个24(或12)
Clock
- VERILOG描写的数字时钟，经验证测试通过可以很好地工作！-Digital Clock desinged by verilog,which operates correctly.
clock
- 基于fapa应用verilog语言实现多功能数字时钟-Verilog language based fapa application multifunction digital clock
mydesign_DPLL
- 实现了数字锁相环设计，可以用于信号的时钟提取供本地时钟使用-the design introduced a method to use DPLL,we can get the local clock from the signal
clock3
- 一个带闹钟的分为12 和24 小时的数字时钟。只有24小时有闹钟，都是原件例化，用的是位置关联-With alarm clock into a 12- and 24-hour digital clock. Only 24-hour alarm, all of the original case, the location associated with the
clock_top
- 基于cx200a的fpga的数字时钟系统的设计，-Fpga based cx200a of the digital clock system design,
beep_key
- 基于VHDL硬件描述语言设计的多功能数字时钟的思路和技巧-VHDL hardware descr iption language based on multi-functional digital clock design ideas and techniques
daima
- VHDL数字时钟而服务而过分为二分给他沃尔夫-VHDL digital clock
digital-clock-design
- VHDL语言编写的数字时钟设计程序，含源代码和波形仿真，还有顶层电路设计。-The VHDL language of the digital clock design procedures, including source code and the waveform simulation, but also the circuit design.
verilog
- verilog语言编写的数字时钟程序，有计时，校准等功能-verilog language digital clock program
digit-clock
- 基于quartus II 软件用vhdl语言写的数字时钟实验 源代码、最终生成文件全程奉献-Quartus II software-based language used to write the vhdl source code digital clock experiment, the resulting file full dedication
FPGA-clock
- 用FPGA编写程序实现数字时钟的设计，具有计时、秒表及闹钟功能-FPGA programming with digital clock design, with timing, stopwatch and alarm functions
FPGA_clock
- 基于FPGA的多功能的数字时钟！能够显示时，分，秒，日期！-FPGA based multi function digital clock! Can display hours, minutes, seconds, date!
digital_clock
- 本程序用VHDL语言实现数字时钟的功能，适用于ISE软件-This VHDL program has the function of digital clock and is suited for ISE software
EDA-shuzizhong
- 用EDA软件实现数字时钟的设计，提供详细的代码-Using EDA software to realize the digital clock design, with detailed code