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shuzizhong
- 基于VHDL的数字钟的设计,本文给出了详细的代码,直接可用!-VHDL-based digital clock design, this paper presents a detailed code, directly available!
clock
- 数字钟,用VHDL 编写。具有计时,校时(调分调时),报时功能-Digital clock, written with VHDL. With time, school time (when the tone on tones), timekeeping function
final
- 基于VHDL的数字钟实现,适用于大学数字电路与逻辑设计课程的期末考试或实验内容-VHDL-based digital clock implementation
0710200134
- 本文介绍了一个多功能电子钟的设计方案。该方案具有计时、整点报时、校时、校分、闹钟等多项功能。此方案基于Altera 公司的 Cyclone 芯片及Quartus II 7.2 软件。整体设计采用自顶向下的设计思想,大量使用了器件模块化操作。本文对于研究数字钟及扩大其应用,有着非常现实的意义。-This paper describes a multi-clock design. The program has the time, the whole point of time, school ho
shuzizhong_VHDL
- 用VHDL语言写了数字钟程序,并用数码管显示,经过硬件调试可行-timer clock
shuzizhong
- 多功能数字钟,可调时间,可报时,可控制,可以按键显示-duo gongneng shuzizhong
EDA4
- 数字钟设计:实现动态数码管显示时分秒; 可以预置为12小时计时显示和24小时计时显示;一个调节键,用于调节目标数位数字。对调节的内容敏感,如调节分钟或秒时,保持按下时自动计数,否则以脉冲计数。 -Digital clock design: dynamic digital display, hour can be preset to 12-hour time display and 24-hour time display a regulatory key target for reg
DigitalClock
- 用EDA仿真软件做的一个数字钟设计实验,能够实现小时、分钟、秒的60进制计时。是我的课程设计全部源码哦~-EDA simulation software to do with a digital clock design experiments, to achieve hour, minute, second of 60 Hex timing. Curriculum design is all the source code of my oh
VHDL
- 各种vhdl程序,包括基础程序数码管,led,串口等和综合程序数字钟等。-Vhdl various procedures, including procedures based on digital control, led, serial port and integrated programs such as digital clock and so on.
LED
- led数字钟实现时、分计时大学法规定地方官方宣传大概-led clockadasdasdcdgh吃饭不构成vbn
VHDLDigitalClock
- 数字钟的VHDL语言实现基本功能,包括 1、24小时计数显示; 2、具有校时功能(时,分) ; 附加要求: 1、实现闹钟功能(定时,闹响); -Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1
SHUZIZHONG
- 基于VHDL语言的数字钟的,包括显示,按键控制等-无
digital_clock
- 用Verilog HDL 设计一个多功能数字钟,包含以下主要功能: (1) 计时,时间以24小时制显示。 (2) 校时, (3) 跑表:启动、停止、暂停 -Verilog HDL design with a multi-functional digital clock, includes the following main functions: (1) time, time to 24-hour display. (2) school, (3) stopwatch: start
DigitalClockBasedonVHDL
- 基于VHDL编写的数字钟,可以设置时间、闹钟,实现报时等功能。-Written in VHDL-based digital clock, can set time, alarm clock, to achieve timekeeping functions.
clock
- 多功能数字钟,、在Quartus 2环境中编译通过; 4、仿真通过并得到正确的波形; 5、给出相应的设计报告 -clock
ISE_lab16
- 使用VHDL语言设计数字钟。 数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components
mclock
- 用VHDL编写的带闹钟报时功能的数字钟 ,现代数字系统设计作业。 采用文本图形混合输入,在maxplus2 10.0运行通过-Written by VHDL figures with alarm chime clock, modern digital system design work. Graphics mixed with text input, run by the maxplus2 10.0
fpgaclock
- 数字钟小程序,FPGA程序,用VHDL编写的源程序-failed to translate
cpclock
- 能显示时、分、秒的简易数字钟,可以同时在6个共阳极数码管上显示,能实异步清0。代码部分-Can display hours, minutes, seconds, simple digital clock, can in the six common anode LED display, to implement asynchronous to 0. Code section
shuzizhong
- 基于VHDL的数字钟,可以整点报时和校准时间-VHDL CPLD