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数码管扫描显示转换模块
- 数码扫描显示转换模块，可以对数码内容进行扫描，同时可进行转换-digital scan conversion modules, the digital content can scan, which can also be converted
在六个数码管滚动显示自己的学号（六位）
- 在六个数码管滚动显示自己的学号（六位），每隔一定时间循环移位一次，学号为奇数则左移，学号为偶数则右移。间隔时间可由开关选择1秒，2秒，3秒和4秒。-In the six LED scrolling display their student number (six), rotate once every certain period of time, learning number is odd, then the left, student number is even, then the r
shuma.rar
- 数码管动态显示程序，verilog的，已经调试成功,verilog
dled.rar
- VHDL语言，动态数码管扫描显示。包含分频程序和扫描键盘程序。,VHDL language, dynamic digital tube display scan. Frequency Division contains the procedures and procedures for scanning the keyboard.
shumaguan.rar
- 用CPLD驱动数码管，实现从0000计到9999，数码管是用动态显示，程序用VERILOG完成的,CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG
fsmled
- verilog语言, 状态机实现数码管显示 -This uses verilog language to make state machine realization of digital control
NIOS_TFT
- 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
datashow
- 本程序是一个用VHDL编写的数码管扫描显示控制器的设计与实现的程序，仅供学习。-This procedure is a VHDL prepared using digital tube scanning display controller design and implementation of procedures for learning.
calculator
- 用VHDL在quartus2下实现的计算器。输入为4*4矩阵键盘，输出为共用数据线的数码管。可以实现简单数学运算、逻辑运算、进制转换、连续运算等功能。-Using VHDL in quartus2 achieve calculator. Input 4* 4 matrix keyboard, the output data lines for sharing of digital control. Can achieve a simple mathematical operations, log
verilog
- verilog实现的数字频率计8位数码管输出显示同时矩形波分档输出-verilog implementation of digital frequency meter
freq
- 智能频率计 1. 频率测量范围为1Hz~1MHz 2. 当频率在1KHz以下时采用测周方法 其它情 况采用测频方法.二者之间自动转换 3. 测量结果显示在数码管上,单位可以是Hz（Ｈ）、 KHz（ＡＨ）或MHz（ＢＨ）。 ４. 测量过程不显示数据，待测量结果结束后，直接显示结果。 -Intelligent frequency meter 1. Frequency measurement range of 1Hz ~ 1MHz 2. When th
VHDL
- DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage si
Mars_EP1C6F_Interface_demo(VHDL)
- FPGA开发板配套VHDL代码。芯片为Mars EP1C6F。一些接口通信的源码。包括7段数码管、I2C通讯等。-FPGA development board support VHDL code. Chips for the Mars EP1C6F. Some of the source interface. Including 7 digital tube, I2C communications.
myled4
- 四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL
Quartus4
- 1实现六个数码管串行扫描电路 2六个数码管滚动显示电路-1 to achieve the six digital control circuit 2, six serial digital scanning tube rolling display circuit
DE2_LCM_CCD
- DE2 CCD数码相机源代码，下载即可使用。方便学习。-DE2 CCD digital camera source code, you can use to download. Facilitate learning.
NIOS_seddisplay
- NIOS七段数码管显示系统设计，包括完整的硬件合软件设计-NIOS Seven-Segment LED Display System Design
DVP3000J
- ET6202驱动数码管显示，每个按键显示一个数字，用AT89S51作MCU-ET6202-driven digital display, each button displays a number for the MCU to use AT89S51
8个数码管显示数码管动态扫描显示
- 共阳极数码管显示1,2,3,4,5,6,7,8。FPGA可直接编译。
数码管显示
- 在FPGA EGO1的口袋平台上实现数码管滚动显示学号的功能(Rolling on the digital tube to display the school number)