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kt3tuo
- 基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯-Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
SOPC
- 能显示时、分、秒，24小时制；可设定夜间某个时段不报时；-Can display hours, minutes, seconds, 24-hour system can set a time at night is not the newspaper
jiaotongdeng-
- 可以实现，交通灯的模拟，自己设定中间时段长短-Can be achieved, the simulation of traffic lights, the middle of their set length of time
digital
- 原创-verilog数字钟-基于quartus-显示时分秒-整点报时-设置时段不报时-欢迎下载-Original-Verilog digital clock-based on quartus- Displays minutes and seconds- the whole point of time- set time period does not chime- Welcome to download
shi-zhong
- 基于fpga的时钟设计，包含报时模块，时段控制，等-Fpga-based clock design contains timekeeping module, time control, and so on. .
EDA-Clock
- 基本功能： 1、输入1KHZ的时钟； 2、能显示时、分、秒，24小时制； 3、时和分有校正功能； 4、当计时器运行到59分49秒开始报时，每鸣叫1s就停叫1s，共鸣叫6响；前5响为低音，频率为500HZ；最后一响为高音，频率为1KHZ； 5、可设定夜间某个时段不报时； 6、设定闹钟。 -Basic functions: input 1kHz clock 2, display hours, minutes, seconds, 24-hour clock 3, hou
TAXI
- VHDL硬件描述语言实现出租车计费器的功能，不同时段，不同行驶状态费用可以调节-VHDL hardware descr iption language taxi meter' s functions, different times, different running state fee can be adjusted