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7led
- 一个最大公约数七段显示器编码VHDL代码设计
gcd
- 欧几里得算法求最大公约数电路的Verilog实现，消耗功率较低-Euclid algorithm for the realization of the common denominator Verilog circuit, lower power consumption
gcd
- 这是一个求最大公约数的verilog源码-this is a verilog source code which can count the greatest common divider .
GCD
- 最大公约数的计算,各个源描述的编译顺序:gcd.vhd,gcd_stim.vhd-The common denominator of the calculation, the various sources described in the order of the compiler: gcd.vhd, gcd_stim.vhd
gcd_disp
- 最大公约数七段显示器编码,各个源描述的编译顺序gcd_disp.vhd,vhdl.vhd,stim.vhd-Seven-Segment Display common denominator coding, various sources described in order to compile gcd_disp.vhd, vhdl.vhd, stim.vhd
exer3
- 3， 采用尽可能少的电路，求出两个在100以内的正整数的最大公约数和最小公倍数。（不许采用mod函数），仿真并综合出电路-3, the circuit using as little as possible, find two positive integers less than the 100 greatest common divisor and least common multiple. (Not allowed to use mod function), and integrated
zdgys
- 利用VHDL实现求两个二十四位二进制数的最大公约数-Use VHDL to find the greatest common divisor of two number
gcd
- 求最大公约数的vhdl 源代码 gcd-gcd
gcd_lcm
- 求两个100以内整数的最大公约数和最小公倍数，只用加法和减法运算-Find the greatest common divisor of two integers less than 100 and the least common multiple, only addition and subtraction
verilog
- Verilog HDL 1.红外线发射调制电路 2.分数分频 3.最大公约数和最小公倍数 4.秒表-1.infra transmission modulator 2.fractal frequency divider 3.maximal common divisor 4.timer
Verilog
- 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
GCD
- Verilog 最大公约数设计RTL级代码和芯片设计图-Verilog GCD Design and synthesis layout
gcd3
- 用verilog代码编写的GCD即找两个数之间的最大公约数的FPGA工程。-Verilog code written with the GCD of two numbers that find the common denominator between the FPGA project.
zheng
- 基于ise实现的求最大公约数。并在modelsim 上实现-base on ise and modelsim .
gcd
- 分别基于功耗优先和性能优先的欧几里得求最大公约数算法 包括说明文档-based performence and power design for gcd cotain the instruction word
GCD_Verilog
- 利用Verilog语言写的采用更相减运算的球两个数的最大公约数-Using Verilog language written using a subtraction ball number two of the greatest common divisor
src
- 自己写的一个求两个32位操作数的最大公约数处理器的verilog代码，采用的是流水线结构-A seek the greatest common divisor of two 32-bit operands processor verilog code pipeline structure
GCD
- 可以很好的实现求解最大公约数，并且语法结构易懂-Good solving the common denominator, and easy to understand
gcd_power
- 用硬件描述语言实现求最大公约数，使用FSM-using hdl implements the gcd with gsm
PipeLine-GCD-DSP
- 流水线结构的最大公约数处理器，处理的数据为32bit,采用64级流水线实现。-A pipeline sturcture GCD DAC, data width is 32bit.