搜索资源列表
dds
- 基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.
HwLog10.rar
- 用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。,It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.
VHDL8
- 一个VHDL拨码开关以及数码管显示的例程，让你更好的明白VHDL查表法的方便，从而减少逻辑单元的使用。-A VHDL DIP switches and digital LED display routine, so you better understand the convenience of VHDL look-up table, thereby reducing the use of logic cells.
dayin
- 该程序利用vhdl语言，采用查表法实现am调制，此方法简洁又有效-The program using vhdl language, using look-up table method to achieve am modulation, this method is simple and effective
FPGASquare-RootRaised-CosineFilter
- 数字通信系统中, 基带信号的频谱一般较宽, 因此 传递前需对信号进行成形处理, 以改善其频谱特性,使 得在消除码间干扰与达到最佳检测接收的前提下,提高信道的频带利用率。目前,数字系统中常使用的波形成形滤波器有平方根升余弦滤波器、 高斯滤波器等。设计方法有卷积法或查表法, 其中: 卷积法的实现,需要消耗大量的乘法器与加法器,以构成具有一定延时的流水线结构。为降低硬件消耗,文献提出了一种分-FPGA Implementation of Square Root Raised Cosine Pu
dds
- 通过查表法，用FPGA实现波形的输出。预先将数据存放在ROM中，依次读取数据并输出。-Look-up table method, the output waveform with FPGA implementation. Advance to data stored in ROM, in order to read data and output.
jiyu-FPGA-chaochengboxinhaochuli
- 了降低超声波流量检测过程中噪声对检测精度的影响，采用FPGA器件构建了FIR滤波器，并提出一种新颖的查表法替代滤波器中的乘法运算-In order to reduce the flow in the process of ultrasonic testing noise on the influence of the precision, based on FPGA device constructed the FIR filter, and put forward a novel queryi
NCO
- 查表法实现NCO数控振荡器，16位频率控制字深度1024，包含ROM表-nco rom
DAIMA-BLACK
- VHDL 语言的 能量感知的基础算法及sin 查表法 HEX，9-256-Energy VHDL language and perception on the basis of the algorithm sin lookup table HEX ,9-256
SPWM
- ALTERA FPGA上采用Verilog语言实现查表法产生三电平SPWM-Produce three-level SPWM by look-up table
DDS
- dds采用查表法的方式实现，有MATLAB取样。基本的方法-DDS is implemented by look-up table, with MATLAB sampling