搜索资源列表
LED
- basys2 流水灯 verilog语言编写-basys2 light water verilog
FPGAVHDL
- vhdl例程代码大全，包含流水灯，数码管，AD,DA转换等-Guinness vhdl code routines, including water lights, digital, AD, DA conversion
liushuidengyouyi
- 此程序是用vhdl语言描写的流水灯程序，功能是流水灯左移-This procedure is used in light water vhdl language to describe the program, the function is left light water
picoblaze
- 基于Nexys3的picoblaze，实现了一个命令菜单，可以控制流水灯，VGA显示，交通灯。verilog，VHDL都有。-Based picoblaze Nexys3 achieve a command menu, you can control the water lights, VGA display, traffic lights. verilog, VHDL has.
Johnson_counter
- 基于FPGA的Jhonson计数器，能用按键控制流水灯-FPGA-based Jhonson counter, can control buttons light water
run
- verilog HDL PARTAN 3E100的流水灯程序-verilog HDL PARTAN 3E100 water light program
run_flash_led
- 用verilog建立一个并行操作的流水灯模块。扫描频配置定为100 Hz，而每一个功能模块在特定的时间内，将输出拉高。-The establishment of a parallel operation of light water module verilog. Scanning frequency configured as 100 Hz, and each functional module within the specified time, the output high.
running-water-led
- 流水灯程序，采用组合逻辑。内有仿真文件。是FPGA开发必须学的一个程序-Light water program, using a combination of logic. There simulation files. Is a program FPGA development must learn
exp5
- 使用状态机实现流水灯流动,可以通过这个例子学习状态机的使用，但如果以此作为流水灯的控制方法则有待商榷。-use state machine realise leds that flow.
run_led
- Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
key_led
- 基于xilinxFPGA测试通过，按键消抖动，verilog编写，控制流水灯-Based xilinxFPGA test, the key jitter elimination, verilog prepared to control water lights
monitoringV5
- 文件的FPGA是基于Xilinx ISE写的，所用开发板为zedboard7020 484系列，完成的功能为：读取XADC里的温度，VCC，并存储到RAM中，通过流水灯实现翻看，读取等功能.-Document is based on Xilinx ISE FPGA wrote, the use of development board for zedboard7020 484 series, completed functions: reading XADC in temperature, VC
Lab5.5_Led_FPGA
- 使用verilog在fpga开发板实现流水灯，包括整个工程文件-This code is used for early learners to study verilog。
led
- FPGA做的led流水灯，quartus搭的nios，计时器每隔一秒led点亮一次，四个流水灯循环显示，适合新手学习-FPGA do led light water, quartus ride nios, timer once every second led lights, four light water cycle, for beginners to learn
liushuideng
- verilog做的流水灯，分频器做半秒的tc，流水灯每半秒流动一次 -verilog do water lights, dividers do half a second tc, light water flow once every half-second
0--9999
- 0--9999，计数数码管点亮，流水灯多种特别流动，流动的间隔时间为1s-0- 9999 count digital tube lights, a variety of special light water flow
lab2_solution
- 基于ANVYL平台的流水灯设计，VHDL-Light water-based platform designed ANVYL, VHDL
water-LED
- 用VERILOG语言实现的LED流水灯实验，通过移位方法实现，代码简单实用。-VERILOG language with an LED light water experiment, achieved by shifting method, the code is simple and practical.
source
- 4个功能模块是独立操作的。由于输出在时间上不同，在肉眼中才会看到流水灯的效果。用现实的角度去思考的话，宛如有四个局内人，无不关系，各自只是按照自己的节奏完成自己的工作。在局外人的眼中，他们如同有默契般，不需要“指挥者”也能完成任务。-led parallel countrol
PWM_LED
- 基于DE2_70平台，编写nios软核c代码，控制流水灯，硬件实现验证通过，适合入门-Based DE2_70 platform, written nios soft core c code, control water lights, verified by hardware implementation, suitable for entry