搜索资源列表
ug_fifo
- 可综合的FIFO存储器，全部在一个压缩包中，测试过，可以使用．-be integrated FIFO memory, all in a compressed package, tested, can be used.
sobel
- 这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。-this is my own preparation for the 256 * 256 size of the image segmentation Edge Detection vhd document in the n
8adderverilog
- 8位加法器的实现，非流水线结构，很不错。我测试过，效率比较高
uart全套vhdl程序
- uart全套vhdl程序 测试过，完全能用
sopc_cpu
- 此例程是基于FPGA的SOPC工程实例，是对CPU操作运用的一个很不错的程序，内有modelsim仿真激励，都是测试过的好程序-This routine is FPGA-based SOPC engineering practice, the use of CPU operation is a very good program, there modelsim simulation stimulus, good procedures are tested
sdram_ctrl1.rar
- FPGA读写SDRAM的VHDL程序，已经测试过,FPGA to read and write the VHDL procedures SDRAM have been tested
sdramcontroller.rar
- FPGA读写SDRAM的VHDL程序(已经测试过),SDRAM read and write the VHDL program FPGA (already tested)
fpga-pwm
- 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and s
RS-code
- 我测试过的！Verilog HDL实现RS编码。-I' ve tested it! RS coding Verilog HDL implementation.
Hardware_Multiplier
- 用VHDL写的硬件乘法器，以及测试过了，一个时钟周期内完成乘法运算。被乘数、乘数的宽度通过通用属性GENERIC参数改变而轻松改变，硬件除法器也快好了。-Written by VHDL hardware multiplier, and tested, and a clock cycle multiplication. Multiplicand, multiplier width parameter changes through the common property of GENERIC an
i2c
- fpga verilog I2c 和 用以DSP mcbsp程序，测试过了-fpga verilog I2c and for the DSP mcbsp procedures, tested the
TEST7
- 这是一个键盘扫描的程序 没有去抖电路 但是还是很好用的 我测试过 很好用的-This is a keyboard scanning procedure did not go to shake or a good circuit but I tested used a very good use
ICX408AL7.5M
- 基于CPLD的CCD驱动程序源码，本人已经测试过，配合单片机控制，就能实现CPLD对CCD的驱动控制和曝光控制-CPLD based on the CCD driver source, I have been tested with single-chip control, you can achieve CPLD driver for CCD control and exposure control
VHDL312vh6
- 包含若干个VHDL小例子，有交通灯，电子琴，简易秒表，等等，交通灯已经测试过，根据自己的需要，稍微改动，很好用！-VHDL contains a number of small example, there is traffic lights, Electronic organ, simple stopwatch, and so on, traffic lights have been tested, according to their own needs, slightly altered,
0
- 用vhdl语言实现4位乘法器，已被测试过，可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of
i2c_AT2402
- 用VHDL语言编写的AT24C02程序，并用数码管显示，本程序已经经过本人测试过，很好用-The AT24C02 is available VHDL language program, and use digital tube display, this procedure has been tested himself, very good to use--
fira
- 这是一个用FPGA中DSP Bulider做的一个FIR滤波器，很好使用，我已经测试过了-This is an FPGA, DSP Bulider used to do a FIR filter, a very good use, I have tested the
dds
- dds信号发生器，硬件测试过，效果良好。文件包含整个fpga开发过程产生的所有文件-dds signal generator, the hardware tested to good effect. File contains the entire fpga development process of all documents generated
step_moto
- 实现步进电机的细分驱动和不细分驱动及选择。正反转，工作使能控制，在开发板上测试过，工作良好-Stepper motor to achieve sub-drive and do not subdivided driving and choice. Positive inversion, work to enable control board in the development of tested, working good
MY_FPGA
- 这是我自己画的FPGA开发板，每个功能都测试过了，硬件是绝对没有问题的-This is my own painting FPGA development board, each feature is tested, and the hardware is absolutely no problem