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04-NEC_2003_C
- 数字相位测量仪(2003年C题),verilog源程序-digital phase meter Problem C (2003), Verilog source code
pinlvji
- 能实现等精度的频率计,测量频率大于1Hz以上的信号,可以测周期,频率,脉宽,占空比。-Equal precision frequency meter measuring frequency is greater than 1Hz or more signal can be measured cycles, frequency, pulse width, duty cycle.
pinlvji
- 1.基本要求 (1)频率测量 测量范围:1HZ~1MHZ,信号为方波等 (2)周期测量 测量范围:1HZ~1MHZ,信号为方波等 (3)具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
ssji
- 1.基本要求 (1)频率测量 测量范围:1HZ~1MHZ,信号为方波等 (2)周期测量 测量范围:1HZ~1MHZ,信号为方波等 (3)具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
ssaszhaohengji
- 1.基本要求 (1)频率测量 测量范围:1HZ~1MHZ,信号为方波等 (2)周期测量 测量范围:1HZ~1MHZ,信号为方波等 (3)具有显示功能。 -A. Basic requirements (1) the frequency of measurement Measuring range: 1HZ ~ 1MHZ, the signal is a square wave, etc. (2) The cycle of measurement Measuring ra
atop
- 该程序可以测量外部频率的频率计电路,包含顶层模块,和底层模块。-The program can measure the frequency of the external frequency meter circuit, including the top-level module and bottom module.
EDA
- 其测量范围为1MHz。量程分10kHz,100kHz和 1MHz三档(最大读数分别为9.99kHz,99.9kHz,999kHz)。 被测信号由信号发生器提供。 -The measuring range of 1MHz. Range sub-10kHz, 100kHz and 1MHz third gear (maximum reading for the 9.99kHz, 99.9kHz, 999kHz). The measured signal from the signal generat
EDAshuzipinlvji
- 1)能够测量正弦波、三角波、锯齿波、矩形波等周期性信号的频率; 2)能直接用十进制数字显示测得的频率; 3)频率测量范围:1HZ~10KHZ切量程能自动切换; 4)输入信号幅度范围为0.5~5V,要求一起自动适应; 5)测量时间:T〈=1.5S;6)用CPLD/FPGA可编程逻辑器件实现 -1) capable of measuring the frequency of the sine wave, triangle wave, sawtooth wave, rectangular wave p
AD_change
- 利用ADC0809实现模拟与数字的转换,并在数码管上显示实际的数据,测试过与实际电压表测量的模拟数据精确-Use ADC0809 analog and digital conversion, digital tube display the actual data, tested the precision measurement of analog data with the actual voltmeter
pinlvji
- 使用verilog语言设计一个3位十进制数字式频率计,其测量范围为1MHz,量程为10kMz,100kMz和1MMz三档(最大读数分别为:9.99kMz,99.9kMz和999kMz)-Use verilog language, design a three decimal digital frequency meter
digital_freq
- 数字频率计,具有自动校验和测量两种功能,即能用标准时钟校验、测量精度。-Digital frequency meter, automatic calibration and measurement of two functions, that is, use the standard clock calibration, measurement accuracy.
Digital-frequency-meter
- 具有测量和自动校验功能的十进制数字频率计。-Measurement and automatic calibration function decimal digital frequency meter.
hill
- 本文介绍基于NiosII系统的家庭健康专家的设计。该设备定位于医疗保健领域内的家用电子产品,为家庭各个成员提供健康测量、健康教育、科学锻炼与数据综合等功能。设备采用了uC/OSII实时操作系统,可灵活的自定义外设,实现了大容量的数据存储,友好的用户界面和可靠的系统控制。-This article describes the design based on NiosII system of family health experts. The positioning of the device i
shiyan
- 能够测量出方波的频率,其范围50Hz~50KHz。 要求测量的频率绝对误差±5Hz。 将测量出的频率以十进制格式在实验板上的4个数码管上显示。 测量响应时间小于等于10秒。-Able to measure the square wave frequency, its range 50Hz to 50KHz. Require the measurement of the absolute frequency error 5Hz. Will measure the frequency i
PMSM-coder-angle
- 永磁同步电机编码器角度测量程序,verilog编程-The PMSM encoder angle program
equalfreq
- 采用verilog语言实现的等精度频率测量,在FPGA仿真通过-design of Equal precision frequency measurement with verilog HDL in FPGA
exp12
- 本实验要完成的任务就是设计一个频率计,系统时钟选择核心板上的50MHz的时钟,闸门时间为1s(通过对系统时钟进行分频得到),在闸门为高电平期间,对输入的频率进行计数,当闸门变低的时候,记录当前的频率值,并将频率计数器清零,频率的显示每过2秒刷新一次。被测频率通过一个拨动开关来选择是使用系统中的数字时钟源模块的时钟信号还是从外部通过系统的输入输出模块的输入端输入一个数字信号进行频率测量。当拨动开关为高电平时,测量系统数字时钟信号模块的数字信号,否则测量从外部输入的数字信号。-To complete
VHDL
- 电路主要由七个模块组成:时钟产生模块用于产生1KHz的扫描时钟和1Hz的时钟;二分频模块用于对1Hz的时钟信号二分频;测量/校验选择模块用于功能选择;计数模块用于对输入的cp信号计数;送存选择、报警电路根据选择的量程送存信号并显示单位,在超出所选量程时报警;锁存器锁存要显示的结果;扫描显示模块在1KHz的扫描时钟下,依次扫描三个数码管,并显示结果。-The circuit consists of seven main modules: clock generation module is use
Digital-frequency-meter
- 设计了一种基于EDA的数字频率计,它主要采用的是测频法测量通常情况下,计算每秒内待测信号的脉冲个数,即闸门时间为1 s。所得的计数个数即为频率,然后输出给数码管显示。-It introduces a design based on digital frequency meter EDA, it mainly adopts frequency measurement method for measuring the is usually calculated per second, for the
tsxt4
- 频率计,使用Fpga的语言设计实现对频率的测量,可以通过自己修改,平台式ED2 开发板》-Frequency meter, the use of Fpga language design and implementation of frequency measurement, can modify their own, platform type ED2 development board "