搜索资源列表
shifter
- 用vhdl实现双向移位寄存器 仿真环境MAXPLUS-II，QUARTUS--bidirectional use VHDL simulation environment shift register Segments-II, QUARTUS-
CNT_24
- 用vhdl实现24小时计数器，方法简单实用。 仿真环境MAXPLUS--use VHDL to achieve 24-hour counter, simple and practical method. Simulation environment Segments-
pulse_change
- 用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
clock_time
- 本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
USB枚举
- ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
一个VHDL实现的测频计
- 一个vhdl实现的测频计,开发环境为任何支持vhdl语言的厂商提供的开发环境 -VHDL achieve a frequency measurement of dollars, development environment for any VHDL language support for manufacturers of the development environment
路*通灯
- 个人硬件课程设计，简单实现了FPGA平台的路*通灯管理，开发环境为MAX+plus-individual hardware curriculum design, a simple realization FPGA platform junction traffic lights management, development environment for MAX plus
ispLEVER培训教程
- ispLEVER是LATTICE的CPLD、FPGA继承开发环境-ispLEVER CPLD, FPGA development environment succession
avalon_slave_pwm
- NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
hello_2pwm
- NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
reg_file
- NIOS环境PWM的USER LOGIC实例3-NIOS environment PWM USER Logic Example 3
NIOS PWM HAL
- NIOS环境PWM的USER LOGIC实例4-NIOS environment PWM USER LOGIC example 4
NIOS PWM inc
- NIOS环境PWM的USER LOGIC实例5-NIOS environment PWM USER Logic Case 5
8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
DEMO22
- ＶＨＤＬ源程序，ＭＡＸＰＬＵＳ 环境下运行，电梯控制系统-VHDL source code, under Operation Converter, elevator control system
DEMO21
- ＶＨＤＬ 在ＭＡＸＰＬＵＳ环境下运行， 自动升降几-VHDL environment in the run, several automatic movements
alu_inverter
- 4bit ALU 利用vhdl语言编写的4位ALU 开发环境是在windows下-Band ALU using VHDL language prepared by the four ALU is a development environment under Windows
66_FIR
- 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现.rar
- ad9777的测试程序，对SPI进行初始化，运用ISE环境，成功地进行综合和实现
ispLEVER是LATTICE的CPLD、FPGA继承开发环境
- ispLEVER是LATTICE的CPLD、FPGA继承开发环境，ISPLEVER许可文件--ISPLEVER6.0-7.1的注册机,ispLEVER is LATTICE of CPLD, FPGA development environment succession, ISPLEVER license file- ISPLEVER6 .0-7.1 the Zhuceji