FPGA verilog用移位相加的方式来实现8位的乘法器-FPGA verilog With shift and add a way to achieve 8 multiplier

8bit 无符号串联乘法器，由状态机实现，用相加与移位实现乘法功能。-Unsigned 8bit serial multiplier, the state machine implementation, realized by adding the shift multiplication function.