有符号定点数加法运算代码，使用Verilog HDL语言实现(Code writing in Verilog HDL,to solve the problem about signed number calculation.)

对基于符号LMS算法的自适应均衡器进行仿真。要求分别进行算法的性能仿真、生成FPGA测试用的输入信号、仿真权值在运算过程中的数据范围(The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the da