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- vhdl 除法器 eda课程设计用。 设计一个两个五位数相除的整数除法器。用发光二极管显示输入数值,用7段显示器显示结果十进制结果。除数和被除数分两次输入,在输入除数和被除数时,要求显示十进制输入数据。采用分时显示方式进行,可参见计算器的显示功能。-divider vhdl eda curriculum design purposes. Design a two five-digit integer divider division. Enter the value with the lig
calculator_final
- 清华大学电子课程设计:Verilog,QuartusII可正确运行,可下载到FPGA上,音乐计算器,完成两个三位数的运算,有注释,很强大-Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !
project1
- 音乐计算器的设计与实现。完成加减与或比较计算,能显示进位借位零位,能根据结果的正负发出两首不同的音乐。(Design and implementation of music calculator. Complete addition and subtraction and comparison calculation, can display carry and borrow zero, can send out two different music according to the posi