搜索资源列表
trafficled
- 数字电路的交通灯设计，具有主道和旁道两个不同时间的控制处理，使用vhdl语言编译，附有完整的报告及代码，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design of a traffic light with a main road and bypass roads are two different time control processing, using vhdl language compiler, with full r
VHDL_digital_lock_design
- VHDL课程的源代码数字密码锁的设计与实现的实验报告，内附源代码-VHDL source code for the course digital code lock design and implementation of the experimental report, included the source code
ROM_based_sine_wave_generator_VHDL_design
- VHDL基于ROM的正弦波发生器的设计的实验报告，内附源代码-ROM-based sine wave generator VHDL design of experiment reports, included the source code
VHDL_design_of_sequence_detector
- VHDL中序列检测器的设计的实验报告，包括源代码-VHDL in the design of sequence detector test reports, including the source code
7-segment_digital_tube_decoder_design
- VHDL中7段数码管译码器设计与实现的实验报告，包括源代码-VHDL in the 7-segment digital tube decoder design and implementation of the experimental report, including the source code
tiaopin
- 开题报告，基于Quartus ii的DDS设计和实现。-Opening report, based on Quartus ii of DDS design and implementation.
MultiCLKCPU
- 本设计实现了多周期CPU的设计，运行环境是quatrus2；该多周期CPU可以处理22条32位指令（具体指令见源码，绝不坑人）。压缩包内含有源代码，程序模块表和实验报告以及详细的设计图，是学习verilog的好材料啊。-The Design and Implementation of a multi-cycle CPU design, operating environment is quatrus2 the multi-cycle CPU can handle 22 32 instructi
FPGA-clock
- 基于VHDL的时钟设计（de2开发平台），内含源代码，各模块的时序仿真图，结构原理图，以及完成报告。供大家参考学习。-VHDL-based clock design (de2 development platform), contains the source code, simulation charts of each module, structure diagram, and the mission report. For reference study.
fpga111
- 基于FPGA步电机毕业设计的开通报告，共享给大家，希望有用-Step Motor Based on FPGA opening graduation report, shared with us the hope that useful
pinball_vhdl
- 学长数字系统设计的技术报告，做的是一个点阵实现的弹球游戏，自己做这个的时候也是参考这份资料的，非常具有参考价值-Digital System Design Mentor technical report, do a lattice realization of pinball games, their is also a reference to do this when the data have great reference value
elevatorcontroller
- 用VHDL语言实现电梯控制器的设计，能够很好地实现功能，并且包含实验报告-VHDL elevator controller design,experiment report
Alteradesigndocument
- 本实验程序每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-The experimental procedure for each project examples include the works of the project file, source documents, reports and other documents file and generate th
Example-b3-1
- 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the sof
Example-b8-1
- 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the sof
Example-b8-2
- 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the sof
Example-b8-3
- 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the sof
Example-b8-4
- 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the sof
Example-b8-5
- 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Each project examples include the project files of the project, source files, report files and generate the results files, the reader can use Quartus II or the sof
CLOCK-ON-ALTERA-DEV-NOARD-RONTEX
- 这是我上电子线路设计课程时自己写的数字钟设计的整个工程.网上下载安装quartus II软件后双击clock.sof打开调试.若软件说没有权限,请删除db文件夹后再试. 文件夹中附带我的实验报告,其中详细讲解了我的设计思路\软件架构\可能出现的问题等等. 调试步骤就不讲了,管脚分配请网友自行完成. 开发板 Altera Cyclone II EP2C35F672C6 软件平台 Quartus II 语言 verilogHDL-These are all the project
EDACLOCK
- 一份关于EDA设计数字时钟的报告，与大家分享，希望对大家有帮助-EDA design of a digital clock on the report, to share, we want to help