搜索资源列表
SDH_module
- SDH帧同步头的检测,并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
project
- 在Spartan-3E FPGA开发板上做的一个小项目--带语音功能的计算器,并且通过VGA接口在显示器上显示图形界面。涉及到ps2键盘模块,VGA显示模块,picoblaze汇编,串口收发模块。-In the Spartan-3E FPGA development board to do a small project- a calculator with voice capabilities, and VGA interface, through the graphical interfac
ac_link
- 硬件电子琴 语音通信 fpga 三个模块 speaker tone note music-Fpga hardware keyboard voice communications speaker tone note music of three modules
verilog
- verilog 一些语音模块 方便平时应用-verilog Module some useful speech module
yuyin_jiami
- 基于quarusII仿真软件,进行模块化设计,设计达到的目的是对进来的语音信号进行加密处理-Based on quarusII simulation software, modular design, designed to meet the incoming voice signal is encrypted
Freq_gen
- VHDL语音写的标准分频模块,在vivado开发环境下运行-VHDL voice write standard frequency module, run in vivado development environment
parameter_uart_rx
- 串口接收模块,可以通过parameter,参数化配置传输速率、传输位宽和校验。采用Verilog语音编程实现。使用者根据串口的要求配置好参数,并根据缓冲的大小配置FIFO就可以使用。对帧错误(停止位不为高),检验错误和读FIFO超时(FIFO满的情况下,有新的数据到)等现象进行了检查。(UART serial receiver module, through parameter, configuration parameters of the transmission rate, Data wi
bus
- 公交车系统基于FPGA芯片的基础上,增加了数码管显示模块、语音自动报站模块、红外通信模块。站牌系统采用以FPGA为核心的主控芯片,增加液晶显示模块、红外通信模块、RS232总线模块、指示灯显示模块等。(The bus system is based on FPGA chip. It adds digital tube display module, voice automatic reporting module and infrared communication module. The bu