搜索资源列表
in-ModelSim-and-Xilinx-lib
- 在ModelSim SE中配置Xilinx的库函数 在Modelsim的安装根目录下新建一个文件夹,用来放xilinx的各个库文件,故可以起名 xilinx_lib。类似于Xinlinx的安装文件:\..\\Xilinx\verilog\src中的各个库文件,在xilinx_lib文件 下新建各个文件夹,命名规则为:若src中的文件夹名为unisims,则在xilinx_lib文件夹下新建 为unisims_ver的文件夹,与此雷同,新建名为simprims_ver、Xilinx
MMU-and-PTS-table
- 1. 附件中是对嵌入式底层开发中常见的MMU配置问题做一个简单的描述; 2. 分析过程是以Samsung 2450处理器的官方BSP中U-Boot代码为例进行的; 3. 如果大家有觉得技术细节上有讨论的地方,可以发邮件到guopeixin@126.com一起来讨论,-the document describes the MMU by taking u-boot code in samsung bsp
leon
- LEON处理器,开源。可配置后下载到FPGA。一种开源处理器。航天应用广泛。-LEON processors, open source. Can be configured to download to the FPGA. An open source processor. Wide range of aerospace applications.
EP2C8_PER_lcd1602
- EP2C8Q208,控制1602LCD的Verilog程序,针对不同的板子,引脚配置需要修改一下-EP2C8Q208, control 1602LCD the Verilog program, for different board, pin configuration need to modify the look
FPGA1
- 用CPU配置Altera公司的FPGA1-CPU configuration with Altera Corporation FPGA1
FPGA2
- 用CPU配置Altera公司的FPGA2-CPU configuration with Altera Corporation FPGA2
FPGA3
- 用CPU配置Altera公司的FPGA3-CPU configuration with Altera Corporation FPGA3
FPGA4
- 用CPU配置Altera公司的FPGA4-CPU configuration with Altera Corporation FPGA4
URAT-hdlVHDL
- URTA 各种功能的时序仿真 包括配置 发射接收数据-URTA timing simulation of various functions, including transmitting and receiving data configuration
Ths1207
- VHDL实现Ths1207控制器,根据硬件电路对THS1207进行配置,并读取AD转换结果。-VHDL implementation Ths1207 controller, according to the hardware circuit configuration of the THS1207, and read the AD conversion result.
ex9_cof_M4K_test1
- 这是一个基于M4K块得单口RAM配置仿真实验程序-This is an M4K block was based on a single-port RAM configuration simulation program
dsp-config-fpga
- TI 6713通过spi口配置fpga的源代码。-program for TI S 6713,used for configure of FPGA BY SPI INTERFACE
PICdpjpwm
- PIC单片机PWM模块应用实验程序,包含系统配置、-中断服务程序, 使用PIC16F887芯片,输出50khz占空比50 的方波 -PIC microcontroller PWM module application experimental procedures, including system configuration,- interrupt service routine, use the PIC16F887 chip, a 50 duty cycle output 50khz sq
PLL
- 9s12锁相环配置程序,1.5倍频。编译环境Codewarrior4.6-9s12 PLL configuration program, 1.5 octave. Build environment Codewarrior4.6
mb_support_sram
- 配置MB软核使其支持,SRAM并在此基础上做UART测试,文章(我写的呵呵)详细的讲了如何从最对SRAM时序进行配置,如何设置相应参数,如何生成硬件平台,实在是入门必备。-configure the MB ip core to support SRAM .and ,do a test with dsp uart
fpgaconvert
- 将xilinx 的fpga配置bit文件转换为c语言文件,通过cpu配置fpga-translate?i can t
ps2verilog
- PS2接口的控制配置程序,特权同学原创经过调试完全好用 欢迎下载,-ps2 interface control configuration procedures,privileged students to original
termination
- FPGA端口电平配置的工程文件,可以实现不同的端口配置,包括PECL,TTL,LVDS等,关键是看引脚分配的.UCF文件-FPGA termination,pull-up,pull-down
Reading-User-Data-from-Proms
- FPGA的配置中,从Flash中读写用户数据,包括VHDL、Verilog程序-in configuring FPGA,reading and writing user data from flash,including the VHDL and Verilog code
Using-JTAG-PROMs-for-data-storage
- Xilinx FPGA的配置中,从Flash中读写用户数据,包括VHDL、Verilog程序-in configuring Xilinx FPGA,reading and writing user data from flash,including the VHDL and Verilog code