搜索资源列表
FPGA_SSI
- 文档中的verilog代码实现了FPGA与SSI总线的数据协议链接-Verilog code in the document of the FPGA data bus protocol and SSI links
Tetris-game-based-on-FPGA
- 在FPGA开发板上实现俄罗斯方块游戏的功能,可以链接电脑显示器并使用电脑键盘来控制。-A Tetris game based on FPGA
CPU
- quartus7.2下以VHDL编程,分为多个模块,在链接原理图中编译。-quartus7.2 next to VHDL programming is divided into multiple modules, compile the schematic in the link.
XilinxisdisclosingthisSpecification
- Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”,概述 Texas Instruments EMIF。 ? 第 2 章“Virtex-II 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000 EMIF 连接到 Virtex?-II 系列或 Spartan?-3 FPGA 的实现。 ? 第 3 章“Virtex-4 FPGA 到 EMIF 的设计” 描述将 TI TMS320C6
EDA
- 以上资料是是有关于FPGA芯片与硬件的链接原理图,对开发FPGA有很重要的作用。还有一些相关软件程序供参考-The above information is on the FPGA chip and the hardware link diagram, on the development of FPGA a very important role. There are a number of related software programs for reference
Based-on-the-ARM-embedded-system
- 基于ARM的嵌入式系统,涉及到软件设计的启动代码、实时操作系统、链接定位和调试技术.rar-ARM-based embedded system software design involves the startup code, real-time operating system, links to locate and debug technology. Rar
rs232top
- 链接 rcv 和txm的测试模块 验证 接受 和 传输模块功能-Links rcv and txm test module validation capabilities to receive and transmit modules
MIPS
- 用verilog语言描述的CPU各部分及相关链接-It about CPU s component and relationship which use verilog
8b10_enc
- 8B10B是应用最广泛的编码技术。它被用于串行连 接SCSI、串行ATA、光纤链路、吉比特以太网、XAUI(10吉比特接口)、PCIExpress总线、InfiniBand、 SeriaRapidIO、HyperTransport总线以及IEEE1394b接口(火线)技术中。-8b/10b has been widely adopted by a variety of high speed data communication standards used today and should
DSP_cpld
- dsp控制cpld的代码,包括cpld内部逻辑和与外部的链接引脚-the dsp control the cpld code, including the cpld internal logic and external link pin
sgmii_latest[1].tar
- 这个工程应用于千兆网传输的物理代码子层,同时也用于SGMII接口。两者不同之处是自动协商时链接定时器和控制信息。-This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS.
DM9000A
- DM9000A 链接FPGA接口设计及NIOS驱动-DM9000A FPGA interface for NIOS timescope
gtx_interface_ip
- 高速串行设计FPGA-GTX IP设置生成,可动态配置速率2.4Gbps,1.2Gbps,0.6Gbps,自适应链接-High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
gtx_drp
- 高速串行设计FPGA-GTX IP设置生成drp模块,可动态配置速率2.4Gbps,1.2Gbps,0.6Gbps,自适应链接-High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
keyboard
- 通过ps2口实现键盘的链接,对FPGA进行输入。(Through the PS2 port to achieve the keyboard link, the FPGA input.)