搜索资源列表
8255new
- vhdl实现8255,可重用，ALATEK公司提供验证，用说明文档-achieve VHDL 8255, reusable, ALATEK companies to provide certification, with documentation
Xilinx公司网站下的SDRAM Controller的参考设计
- Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated
arbit
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
backward
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
bidir
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
bin2gry
- verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
除法器
- 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。 设计平台：MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Descr iption Language (VHDL) Descr iption division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Pl
ASKDASK
- ask调制，基于VHDL仿真平台，解调同样给出，此程序经过验证-ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
FSKDFSK
- fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use
Visio-绘图21
- 这是asic流程例子.文件内容已经验证过.如有疑问和我联系-This is the process blends example. The contents of the documents has been proven. And I doubt if links
time_clock
- 实用闹钟的verilog代码。不是vhdl的！经过ldv验证-practical alarm the Verilog code. VHDL is not! After certification ldv
lpt03
- 这也是8255的设计,不知道是否好使,希望得到验证-This is 8255 in the design, so I do not know whether the hope of gaining certification
chuzuchejifeixitong
- 出租车计费系统的 实现，已物理验证。程序简洁。-taxi system of billing, physical verification. Simple procedures.
serial_communication
- 串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。-source code, the code used veilog HDL language, and after I repeatedly verified.
ASIC_and_FPGA_Verification
- ASIC/FPGA验证经典资料，英文版，希望大家可以有所借鉴。-ASIC/FPGA verification classic information, in English, I hope that we can learn from there.
verilog
- Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。 Verilog HDL 语言具有下述描述能力：设计的行为特性、设计的数据流特性、设计的结构组成以及包含响应监控和设计验证方面的时延和波形产生机制。所有这些都使用同一种建模语言。此外，Verilog HDL语言提供了编程语言接口，通过该接口可以在模拟、验证期间
SystemVerilog 验证方法学
- systemverilog 验证方法学，夏宇闻版(systemverilog verification methodology)
UVM验证平台搭建
- 搭建uvm验证平台,通用验证平台结构和搭建流程介绍(How to build a common UVM verification platform?An easy and useful method is instroduced here.)
FPGA系统设计与验证实战指南_V1.2
- FPGA系统设计与验证实战，内含各种常见的FPGA程序设计，AD，RS485，以太网等。(130 sets of resume template FPGA system design and verification, including a variety of common FPGA programming, ad, RS485, Ethernet, etc.)
基于ahb总线的sramc设计与验证（SV，uvm）
- 基于ahb总线的sramc设计与验证（E课网）