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Comparators_16B
- verilog 实现 优化的16位比较器 可以输出大于，小于，等于。模块化设计，可扩展为32位-Verilog achieve optimization of 16 compared with the output can be greater than, less than, equal to. Modular design, which can be expanded to 32
BBSdfbdgdr
- 如果遇到MD5加密文件，而又不知道密码的， 请在数据库中换上这组加密的数据吧 16位：7a57a5a743894a0e 32位：21232f297a57a5a743894a0e4a801fc3 那么密码就是admin-if they MD5 encryption, and do not know the password. please database with a group of encrypted data it 16 : 7a57a5a743894a0e 32
crc
- 用Verilog编写crc校验码，包括8位，12位，16位，32位，非常实用
div2
- 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码
divider
- 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。
divider
- 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）
wb_rtc
- // -*- Mode: Verilog -*- // Filename : wb_master.v // Descr iption : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : U
FixToFloat.将16位二进制有符号纯小数转换为32位单精度浮点数
- 将16位二进制有符号纯小数转换为32位单精度浮点数。实际应用时，最好加tsu、tco约束条件，速度会快些。,There will be 16-bit binary decimal symbol is converted to pure 32-bit single precision floating point. Practical applications, it is best to increase tsu, tco constraints, the speed will be faste
Walsh
- 利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码-Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .
quartus
- 基于vhdl语言描述的16*32点阵静态显示程序，分为单板显示和多板显示。-Static vhdl language to describe 16* 32 dot matrix display program, divided into veneer display and multi-panel display.
cymometer
- 8位十进制的频率计 有相关的波形仿真，对相应计数器的修改，可以实现任何进制（如8、16、32）的修改-8-bit decimal frequency include the relevant waveform simulation, the corresponding changes to the counter, any band can be achieved (eg, 8,16,32) changes
spi
- spi控制器，可以自己修改成8/16/32位模式-SPI controller
brentkung_16
- 16位的brentkung加法器树，在xilinx软件下-16-bit brentkung adder tree, under the xilinx software
vhdl-cpu-16-bit
- VHDL processsor 32 bit ALU SRF BUS DATA ADRESS C16 System On Chip Architecture
clk_div2_4_8_16_32_64_128
- Divide by 2,4,8,16,32,64,128 clock divider
Perl_for_CRC
- Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redu
shifter_arm
- 桶形移位器，8位，16位，32位，含ARM桶形移位器。南大计算机系计算机组成原理实验-Barrel shifter, 8, 16, 32, including the ARM barrel shifter. NTU Department of Computer Science Experimental Computer System
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
bch_dec
- BCH编解码 Features : – allows to correct up to 2 errors. – supports 16/32/64/128 bit memories (typical memory word sizes). – operates on complete memory words in a single cycle. – pure combinational logic design-The double error correcting (DE
dianzhao_dianzhen
- 使用altera的MAX2系列CPLD驱动16*32的双色点阵屏，包含“空车”，“重车”，“电召”三个字。driver.v文件用cpld驱动了东芝的TC62D748芯片，该芯片常用于扫描点阵的驱动上-The MAX2 series CPLD using altera-color dot matrix display driver 16* 32, with " empty" , " heavy vehicles" , " on-call" in t