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vhdl_jishuqi
- 一路24位计数器,cpu可直接读写计数器的计数值.
24_bit_register
- 自己使用VHDL语言编写的24位寄存器.主要用于DDS中-24bit_register
PCM1770
- 24位AD PCM1770的VHDL控制模块，经实践检验可用-24 AD PCM1770 the VHDL control module can be used by the practice
mul24x24
- 24位x24位的乘法器 十分详细24位x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位 x24位的乘法器24位x24位的乘法器-24-bit x24-bit multiplier very detailed 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit 24-bit x24-bit multiplier of the multiplier 24-bit x24-bit
test_in
- 用Verilog编写的产生图像的程序，实现24位数据量产生图像使用DA转换后直接显示-Verilog prepared using the procedure for selecting the images to achieve 24-bit image data generated using the DA converter and directly show the
ddfsdemo
- 直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development enviro
WM_8776
- WM8776控制模块，直接调用为24位、44.1KHZ采样和输出，开启耳机输出。如需更改可将DA，AD和控制模块分别独立-WM8776 control module, a direct call for the 24-bit, 44.1KHZ sampling and output, open the headphone output. For a change can be DA, AD and control modules separately
wallace
- wallace tree 用于16位乘法器的verilog 的 wallace tree代码 -wallace tree verilog file. 16bit wallace tree adder.
chengfaqi
- VHDL24*24位无符号乘法器，采用的是18*18结构-VHDL24*24-bit unsigned multiplier, used in the structure of 18* 18
xueyi
- 实现了数码管显示电路,其中有24位的分频电路，以及数码管的译码电路，最后还有防抖动电路-it show a circle which makes a led
iis_audio
- 24位立体声AD，IIS从模式数字音频数据接收。-24-bit stereo AD, IIS receives digital audio data from the model.
cpld--abcount090418
- epm7128做的24位硬件计数器，频率根据cpld 的晶振决定上限。-epm7128 do 24-bit hardware counter, the oscillator frequency according to the decision cpld ceiling.
filter_stage3
- 滤波器，24位的，可综合代码，易懂好理解-Filters, 24-bit, and can be integrated code, to understand better understanding
24x24-booth
- 可用的24位x24位的booth乘法器的verilog代码-24X24 booth muplily
vga_lcd_latest.tar
- vga lcd 控制器 24位VGA控制，支持12位DVI协议-This embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost
24BitDigIO
- 使用Quartus设计的，串行方式控制，24位数字输入输出的程序。-VHDL 24bitIO
counter_24
- quartusII 9.0 下24位计数器
AB-4F
- 基于CPLD 的四倍频辩向电路设计-24位计数 8位单片机数据输出-Based on the CPLD optical pulse encoder signal multiplier circuit design
EMP7128S
- EMP71285 CPLD实现三通道24位计数器，程序为.VHDL语言实现，同时程序中含有低通滤波算法。-EMP71285 CPLD implementation of three-channel 24-bit counter, the program for the VHDL language, the program contains a low-pass filtering algorithm.
divider
- VERILOG编写的24位除法器代码核，是FPGA或者ASIC设计中的一核心计算模块。-VERILOG written 24 divider code nuclear FPGA or ASIC design in a core module.