搜索资源列表
Verilog-HDL-intra_prediction
- 基于H.264的帧内预测中4×4块的9种预测方法的源程序-H.264 intra prediction based on 4 × 4 block prediction method of the source 9
H[mm.264
- 这是一个描述的文档，教你怎么写Verilog关于H264 的文章那个，考了非常受启发。-This is a descr iption of the document, teach you how to write Verilog that the article on the H264, the test is very enlightening.
DSP_h264_VariableBlockSize
- 這是用verilog HDL實現H.264可變block大小的源碼。為了使其能在FPGA上運作，還加入了我自己的改善。-A verilog HDL code for H.264 with variable block size and my own improvement.
mc_t
- 利用verilog实现H.264中半像素插值功能。30个周期完成一个4x4块儿的横向、纵向和斜向的插值。-Verilog implementation using H.264 in the half-pixel interpolation function. 30 cycles to complete a 4x4 pieces of horizontal, vertical and diagonal interpolation.
mc
- 通过VHDL实现H.264算法中的半像素插值模块。该模块儿可在30个周期内完成一个4x4块的横纵斜插值。-H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.
h264header
- VHDL file for h.264 header
h264intra8x8cc
- H.264 intra predication 8-by-8 block
h264invtransform
- H.264 inverse transform in VHDL
h264quantise
- H.264 quantization block in VHDL.
nova_latest
- h.264完整的解码器，用verilog实现，属于opencores-h.264 full decoder, implemented by verilog, one of opencores
hardh264-src.tar
- VhDl code for low-power design of h.264 system architecture
bb74300fc549
- vhdl code low-power design of h.264 system architecture
RTP_h_264
- RTP 协议是IETF ( Internet Engineering TaskFo rce) 在RFC1889 中给出的, 是专门为交互式音频、视频、仿真数据等实时媒体应用而设计的轻型传输协议。RTP 被定义为在一对一或一对多的传输情况下工作, 其目的是提供时间信息和实现流同步。RTP 通常使用UDP来传送数据, 但RTP 也可以在TCP 或A TM 等协议下工作.对H.264网络开发有何大帮助- The RTP protocol is given in RFC1889 by IETF (I
JointwaveE440
- H.264 1080p60 FPGA/ASIC设计方案-H.264 1080p60 FPGA/ASIC
h.264_vhdl
- 使用Base Profile级别的H.264编码IP核，代码注释相当详细，流程清晰-Base Profile level H.264 encoder IP core, code comments in considerable detail, the process is clear
nova
- 基于H.264 视频编解码 verilog 基于H.264 视频编解码 verilog-Verilog based on the H.264 video codec based on H.264 video codec Verilog
IQIT
- Inverse quantization and DCT for h.264 in verilog
hardh264
- H.264的VHDL描述，可直接在FPGA上仿真运行，也可供学习用-VHDL descr iption of H.264. It can be run on FPGA, and also can be used for study
bluespec-h264_latest.tar
- H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
H.264_verilog
- 基于verilog的H.264视频压缩技术的源代码，包括verilog源代码，以及仿真波形文件，希望对大家有用-verilog h.264