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数据选择器vhd源代码
- 数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。-data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference.
3-8译码器
- vhdl的3-8译码器-instantiate the 3-8 decoder
3-8
- 本文件是利用verilog实现的3-8译码器
VHDL语言实现3—8译码器
- 应用VHDL语言编写的3—8译码器，简单易懂
3_8_decoder
- 利用CASE语句的3-8译码器,3个为数据输入,3个为控制端,分别为S1,S2,S3,输出数据为八位-Use CASE statement 3-8 decoder, three for data entry, three for the control side, namely S1, S2, S3, output data for eight
3-8translater
- 3-8译码器的verilog hdl程序，实现3-8译码功能-3-8 decoder verilog hdl procedures to achieve decoding functions 3-8
3-8-encoder-design
- 通过应用QUARTUSII开发软件对3—8译码器进行设计，给出运行程序和结果-Development through the application of QUARTUSII 3-8 decoder software for design, operational procedures and results are given
3-8xianyimaqi
- VHDL语言实现3-8线译码器，带仿真波形图，和管脚分布图-VHDLLanguage 3-8 line decoder
trans3-8
- 3-8 译码器为常用的组合逻辑电路，其功能是对输入码（3位码）进行译码。-3-8 decoder for commonly used the assembly logic circuit, its function is to input code (three yards) decode.
3-8-decoder-design
- 利用FPGA编程-------实现“ 3－8译码器设计”-3-8 decoder design
3-8
- 8实验八：利用语言实现3-8译码器、8实验八：利用语言实现3-8译码器-8 Experiment 8: the use of language to achieve 3-8 decoder 8 Experiment 8: language 3-8 decoder
3-8YIMAQI
- 基于fpga用verilog的3-8译码器，代码简单明了，适合初学者理解。-failed to translate
3-8decoder
- FPGA/CPLD的开发，基于VHDL语言编写的3-8译码器，供大家参考-Based on the VHDL language 3-8 decoder
3-8
- 3—8译码器,在fpga上实现3,8译码的功能-decoder 3 8
3-8
- 基于verilog的3—8译码器，设计简单，程序清晰易懂-Based verilog 3-8 decoder design is simple, clear and understandable procedures
3-8-assign
- 此程序采用assign语句实现3-8译码器功能，仿真波形正确。-This program uses the assign statement to realize 3-8 decoder function, simulation waveform is right.
3-8yimaqi
- 详细介绍了VHDL中3-8译码器，适合初学者-Details of the 3-8 decoder VHDL, suitable for beginners
3 8
- 用VHDL多种方法实现3-8译码器,元件例化(use VHDL realize 3-8decoder)
3-8译码器VHDL描述
- 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination
VHDL实现3-8译码器
- VHDL实现3-8译码器,使用VHDL硬件描述语言，实现简单的3-8译码器等功能。