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add(FLP).32位元的浮点数加法器
- 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
FixToFloat.将16位二进制有符号纯小数转换为32位单精度浮点数
- 将16位二进制有符号纯小数转换为32位单精度浮点数。实际应用时，最好加tsu、tco约束条件，速度会快些。,There will be 16-bit binary decimal symbol is converted to pure 32-bit single precision floating point. Practical applications, it is best to increase tsu, tco constraints, the speed will be faste
acc32bit 本设计为32位数字相位累加器
- 本设计为32位数字相位累加器，门级描述的Verilog代码。其中，acc32bit.v为顶层文件，full_add1.v为一位全加器的门级描述模块，flop.v为触发器的门级描述模块。-The design for the 32-bit digital phase accumulator, gate-level descr iption of the Verilog code. Which, acc32bit.v as top-level file, full_add1.v as a full
alu
- 这是32位alu的代码，使用verilog写的，包含了简单的运算功能-This is a 32-bit alu code, use verilog to write, and includes a simple arithmetic functions
ALU_ise10migration
- It s vhdl source code for 32 bit ALU.
adder_32
- 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
up_down_counter
- 32 bit up/down counter with count enable based on altera fpga
alu_32_bit
- 一个Verilog语言写的３２位ＡＬＵ的源码。-A language written in Verilog source code for a 32-bit ALU.
2
- 介绍一种软件实现分频器和32位计数器，采用可编程逻辑芯片，运用verilog语言设计出一种分频器和32位计数器 -Introduce a software implementation of divider and 32-bit counter, using programmable logic chips, using verilog language to design a divider and 32-bit counter
ALUALUcontrol
- 实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
32bitBoothmultiplier
- 32位布思乘法器VHDL实现，2个32位数相乘-32-bit Booth multiplier VHDL implementation, two 32-digit multiplication
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
alu32
- 32 bit ALU design using VHDL code for Xilinx ISE Foundation
32-rip-adder
- A ripple carry adder allows you to add two 32-bit numbers
PCI-Target-32-bit-_-66MHz-for-MachXO
- Evaluation Package for PCI Target 32-bit _ 66MHz for MachXO
32-bit-parallel-interger-bit-
- 32 bit parallel integer bit
32-bit-division-design-In-Verilog
- 32位除法器，基于状态机设计，使用Verilog实现-32-bit division based on state machine. Using Verilog
32-bIT-RISC-DOC-a4
- it is 32 bit risc processor code in vhdl
32-bit-RISC
- 基于MIPS指令集的32位RISC处理器逻辑设计的论文，讲的非常详细适合初学者学习。-32-bit RISC processor logic based on MIPS instruction set design paper, speak very detailed is suitable for beginners to learn.