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the verilog source code for being an examble to counts 4-bit number and display in 7-segment.
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bcd to 7 segments display tested on xboard xilinx, all code developed on vhdl
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This extensive proyect turns an FPGA or CPLD into an HC11 simulation. It takes in various opcodes and performs several 8bit operations. The package includes an ALU, UART, RAM module, LCD display and 7 segments as well.-This extensive proyect turns an
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包含一个将二进制加法结果转换为3位BCD码的结构。以方便用七段译码器显示结果。-Convert result of binary adding to 3-digits BCD code, and thus make it easy to display the result with 7 segments decoders.
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ultrasonic meter with srf04 with 7 segments display
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The PS2 scan code is displayed on BCD 7 segments display.
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FPGA bcd 7 segments display example
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BCD to 7 segments display decoder
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