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dds_ise7.1_su
- 用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation.
dds_sin
- 此程序是基于fpga的多功能的信号源程序，能调相，调频，调幅等。-This program is based on fpga s versatile signal source can be PM, FM, AM and so on.
biyeshejiyuandaima
- 智能打铃系统源代码 功能题目名称： 基于FPGA的智能打铃系统的设计 基本要求：1、基本计时和显示功能（用12进制显示）：包括上下午标志； 2、能够设置当前时间； 3、能够实现基本打铃功能，规定： 上午06：00起床铃，打铃5s,停2s，再打铃5s； 下午10：00熄灯铃，打铃5s,停2s，再打铃5s。 重点研究问题：进行模块划分，并实现各模块的功能； -Smart features a bell system source code Title Name:
20090218_Holtek_ht1380
- The HT1380 is a serial timekeeper IC which provides seconds, minutes, hours, day, date, month and year information. The number of days in each month and leap years are automatically adjusted. Also, the HT1380 is designed for low power consu
myclock
- implement a 12-hour clock(This is a 12-hour digital clock, hout designates the hour, mout designates the minute, sout designates the second, and pout designates morning or afternoon. For example, if current time is 3:08:12 pm, then hout = 3, mout = 8