搜索资源列表
fpga(CAN)
- fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。-fpga CAN Bus Controller source, each with explanatory documents on the use of methods.
speedmess
- 此工程项目包可以实现基于spartan3与CAN总线连接后的的汽车时速的模拟仿真。并可计算轮速差的数值。当此数值超出规定的边界值时报警。
I2C_CANBUS_USB_fpga
- CAN总线，Ｉ２Ｃ，ＵＳＢ等的ＦＰＧＡ实现源码
cpld
- 一个关于4CAN卡的硬件程序,用VHDL编写.就是4路CAN总线
can_IPCORE
- CAN总线IPCORE，采用Verilog HDL语言实现。
CAN_controller_ip
- 一个用硬件描述语言编写CAN总线控制器的IP，可以用在NIOS II上。
vga_card
- VGA模块的VHDL代码和软件驱动，可作为外设挂接在Avalon总线上。用一块SRAM作为显存，双缓存切换模式。-VGA module VHDL code and software drivers can be articulated as a peripheral bus in Avalon. As with a piece of SRAM memory, dual-mode cache switching.
canbus
- CAN通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-CAN communication protocol of the hardware descr iption language code for the FPGA bus interface controller development
canbus
- verilog 和VHDL实现的can总线接口代码-the realization of verilog and VHDL code of the can bus interface
opencores_can
- CANIP核 CAN总线以报文为单位进行数据传送,报文的优先级结合在11位标识符中,具有最低二进制数的标识符有最高的优先 级。-CANIPCore
DE2_pio
- altera University Program 的 Avalon总线的IP核，GPIO，可以直接解压以后挂载在Avalon总线上-altera University Program of the Avalon bus IP core, GPIO, after decompression can be directly mounted in the Avalon bus
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
can_latest[1].tar
- CAN，全称“Controller Area Network”，即控制器局域网，是国际上应用最广泛的现场总线之一。最初，CAN被设计作为汽车环境中的微控制器通讯，在车载各电子控制装置ECU之间交换信息，形成汽车电子控制网络。比如：发动机管理系统、变速箱控制器、仪表装备、电子主干系统中，均嵌入CAN控制装置。 -CAN, full name of the " Controller Area Network" , the Controller Area Network, is int
CAN_jiedian
- 都是介绍CAN总线的资料，费了好大劲搞到的，很不错，大家可以分享下-CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
NXPCAN
- 都是介绍CAN总线的资料，费了好大劲搞到的，很不错，大家可以分享下-CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
FIFO_buffer
- 都是介绍CAN总线的资料，费了好大劲搞到的，很不错，大家可以分享下-CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
fog_acc
- 都是介绍CAN总线的资料，费了好大劲搞到的，很不错，大家可以分享下-CAN bus data are introduced, and with great enthusiasm got, very good, we can share with
can
- CAN总线控制器的FPGA源代码，verilog语言编写，支持CAN2.0B协议。对CAN总线开发者非常有用。-FPGA CAN bus controller source code, verilog language, support CAN2.0 protocol B. Developers of CAN bus is very useful.
can-sja1000
- CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。-The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.
CAN_verilog.tar
- CAN 2.0协议控制器，非常全面的控制器Verilog代码，可靠通信，可放心使用。(CAN Bus 2.0 Controller.)