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xiaoche
- 用VHDL编程的智能寻迹小车.驱动电机沿黑线运动,转弯的时候有灯显示.可以综合,实际硬件调试通过.是学习VHDL的很好实例-VHDL programming smart tracking.The car. Electric drives along the black line campaign turning the lights are shown. can comprehensive, practical hardware debugging through. learning is a
vhdl2009
- 并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through) -- The code can now achieve a single byte of Transceivers
FLOOR1
- 电梯的硬件描述语言设计，可以下载测试与仿真，通过EDA开发系统进行调试-lift the hardware descr iption language design, testing can be downloaded and simulation, through the development of EDA system debugging
CLKGDF
- 电子钏的硬件描述语言设计，可以下载测试与仿真，通过EDA开发系统进行调试-electronic bracelets hardware descr iption language design, testing can be downloaded and simulation, through the development of EDA system debugging
EDATRAFFICVHDLLIGHT
- 交通灯的硬件描述语言设计，可以下载测试与仿真，通过EDA开发系统进行调试-traffic lights at the hardware descr iption language design, testing can be downloaded and simulation, through the development of EDA system debugging
first4
- 4人抢答器的硬件描述语言设计，可以下载测试与仿真，通过EDA开发系统进行调试-four Responder hardware descr iption language design, test and can be downloaded simulation, EDA through the development of system debugging
cpu86model
- 关于8086的软核fpga代码，可以直接再fpag的开发板上调试，好用而且是免费的-on the 8086 soft-core fpga code can then direct the development fpag board debugging, handy and free
基于vhdl的二进制转BCD码的设计
- 基于vhdl的二进制转BCD码的设计，已经经过调试，可直接使用,Vhdl based on binary code to BCD design, has been testing can be used directly
system 完成远程通信的整体任务
- Verilog，QuartusII可正确运行，可下载到FPGA上，完成远程通信的整体任务，PC发数据，键盘输入运算符与运算数计算将结果显示在数码管上并返回给PC机，需异步串口调试软件-Verilog, QuartusII run correctly, can be downloaded to the FPGA, to complete the overall task of remote communication, PC send data, keyboard operators and op
lab.rar
- verilog hdl经典例程，全部调试通过,verilogHdl example，all can be used
实现PS/2接口与RS-232接口的数据传输
- 实现PS/2接口与RS-232接口的数据传输， 可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。,The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received ch
uart.rar
- 基于vhdl的串口通信模块，即异步收发机，可实现单片机核fpga的收发串口通信，遵从rs232协议，已经调试过，很不错的资源,Vhdl-based serial communication module, that is, asynchronous transceiver can achieve single-chip transceiver nuclear fpga serial communication, rs232 to comply with the agreement, has be
vhdl语言实现的16乘16的点阵显示设计代码
- vhdl语言实现的16乘16的点阵显示设计代码，调试通过，可借鉴-VHDL language to achieve the 16 by 16 dot matrix display design code, debug is passed, can learn from-vhdl language implementation of the 16 by 16 dot matrix display design code, debug through, we may learn-VHDL langu
music
- 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
PS2
- 此代码是PS2键盘的Verilog程序，键盘的字符可显示在LCD 1602上，经上板调试程序是可行的-This code is a PS2 keyboard Verilog program, keyboard characters can be displayed on the LCD 1602, after the board debug process is feasible
VHDL_code
- 基于FPGA的AD,DA,LCD,LED,CAN,I2C,PS2,VGA以及一些通讯ASK,FSK等的VHDL源程序，所有程序已通过调试，需要的拿走。-FPGA-based AD, DA, LCD, LED, CAN, I2C, PS2, VGA, and some communications ASK, FSK, etc. VHDL source code, all procedures have been debugging, need to take.
can_verilog
- 基于verilog开发的 ｃａｎ 接口 ＩＰ 核已经调试通过附有说明-can ip
12can
- C8051F040的CAN可编程计数器的程序，经调试通过-C8051F040 the UART0 programmable counter program, the debugging
fpga_can_read_write
- FPGA实现can通讯 已经调试成功 mcp1050(FPGA realizes can communication)