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adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
16bit-CLA
- 16 bit carry look ahead adder verilog code
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
CLA.VHDL.CODE
- cla vhdl code with a picture files.
ADDER(2)
- simple 16-bet CLA adder
CLA
- carry look ahead adder
adder-VerilogHDL
- 各种加法器的VerilogHDL语言编写的包括普通加法器，串行进位加法器，超前进位加法器等-Adder VerilogHDL various languages, including ordinary adder, serial carry adder, CLA, etc.
cla-adder
- cla adder code in vhdl
adder1
- adder Ripple Carry Adder(RCA) Carry Look-ahead Adder(CLA) Block Ripple Carry Adder(BRCA) Two-Level Carry Look-ahead Adder-Ripple Carry Adder(RCA) Carry Look-ahead Adder(CLA) Block Ripple
hw5
- 32-bit adder CLA, CSKA adder
code
- 32bit ripple adder, 32bit CLA code
fast-Cla
- fast Carry look ahead adder
CLA_20
- 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code fo
CLA_4
- 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for ver