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mutl16 实现16位移位乘法和除法
- 实现16位移位，可以实现乘法和除法。满足设计要求，实现代码简短，用verilog完成方便，容易操作。-Achieve 16-bit shift, multiplication and division can be achieved. Meet the design requirements to achieve a short code, complete with verilog convenient, easy to operate.
USB2.0IP.rar
- 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档,Complete Verilog language developed by USB2.0 IP core source code, including documentation
DW8051.rar
- Synopsys 公司的DW8051源代码，用verilog编写的，代码很完整，可以仿真，对采用8051核做嵌入式的人很有帮助,Synopsys company DW8051 source code, written with Verilog, the code is complete, can be simulated using 8051 nuclear helpful people who do Embedded
dpll
- dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
Verilog
- fpga使用代码大全，很有用的，，谢谢下载，我没什么说的了，住学习愉快-fpga using the Code Complete, very useful, Thank you to download, I have nothing to say about it, learning to live happily
FSK
- 通信系统的FSK调制程序，比较实用，包括完整的工程-FSK modulation communication system procedures, more practical, including the complete works
SPI_Interface
- SPI接口的vhdl代码，可以实现与单片机的spi通信，完整的工程-SPI interface of the VHDL code can be achieved with SCM spi communication, complete works
The_design_of_MIPS_CPU(VHDL)
- MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
fifotop
- 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
AdderSubtractor
- 4-Bit Adder Subtractor Verilog Code. (Complete project)
4_Bit_Alu_vhdl
- Complete VHDL Code for a 4 BIT ALU PROJECT
i2c
- I2C协议verilog源码，包含完整的测试代码及设计文档。-Verilog source I2C protocol, including the complete test code and design documents.
report-hex-keypad-debouncer
- Quartus Verilog HDL, complete document, having schematics, flowcharts, and Verilog codes for various modules for implementing a hex-keypad, including the important code of DEBOUNCER
vhdl-MIPS
- Quartus-Altera Nios... VHDl based, complete MIPS implementation, document, flowcharts plus code
PN_code_capture_and_tracing
- 一个完整的pn码捕获与跟踪的VHDL源码,并行匹配滤波器捕获,锁相环跟踪.-A complete pn Code Acquisition and Tracking of the VHDL source code, parallel matched filter to capture, phase-locked loop tracking.
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i
reinformationregardingapplicationfee
- paper format that includes Viterbi Decoder complete VHDL code for the document. Nh format paper format that include s Viterbi Decoder complete VHDL code for the document. Nh format paper format that includes Viterbi Decoder complete VHDL code for the
arm9_fpga2_verilog
- ARM9的开发源代码，全套，很难得。现全部共享。 -ARM9 development of source code, complete, very rare. Are all shared.
DE2_TV
- 友晶公司DE2开发板的TV示例完整源代码 FPGA Cyclone-Friends of the crystal of TV company DE2 development board complete source code for FPGA CycloneII sample
usb.vhd
- 用FPGA模拟USB功能，采用VHDL语言编写，代码完善编译通过-USB functionality using FPGA simulation using VHDL language, compile the code complete