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68013FIFOIN
- Verilog HDL 编写的CY7C68013 SLAVE FIFO接口程序，实际测试可用。可以直接跟上位机连接，传输数据。
CY7C68013FPGA
- USB控制芯片cy7c68013与FPGA通过slave fifo方式通信，块传输数据-USB controller chip and FPGA cy7c68013 way communication through the slave fifo, block data transfer
usbin_v1.7
- 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7
SLAVE_FIFO_16BITS
- 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
fifo
- cy7c68013 fifo代码，可实现in配置-cy7c68013 fifo code can be realized in the configuration
CY7C68013 Slave FIFO
- CY7C68013 Slave FIFO