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sdr_c_trl_verilog
- SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
dram_controller
- 用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL descr iption Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.
dram_cntl
- DRAM Controller verilog file
LIP2121CORE_pads_dram_controller
- Pads for DRAM CONTROLLER Verilog MODULE
LIP2131CORE_dram_controller
- LIP2131 CORE Verilog DRAM Controller
mobile_sdram
- mobile DRAM Controller
DDRCHv11
- Source code for ddr2 dram controller for BEEE
sdram controller
- Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and t