搜索资源列表
passlock
- 基于FPGA的电子密码锁的设计，内有Verilog HDL源码和各仿真图像
multifunction_digital_clock_based_on_fpga
- 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等
xd_lcd_comp
- 一款240＊128的LCD模块在ALTERA FPGA NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考
two_d_dct_serial
- altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码，语言是：verilog 性能不错，不过资源消耗有点大，可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be us
FLASH存储器的读写程序
- 此源码为基于FPGA的使用VERILOG编写的FLASH存储器的读写程序。,The source code for the FPGA-based FLASH memory using the VERILOG prepared to read and write procedures.
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
FPGA_DDR-SDRAM
- FPGA对SDRAM的控制，有部分源码，-FPGA SDRAM control, part of the source,...
alteralvds.rar
- 基于altera系列芯片lvds接口的fpga设计 verilog源码,Series altera-based chip interface lvds source fpga design verilog
RX
- 1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
verilogsram
- FPGA开发板上的VerilogHDL编写的SRAM读写试验程序, 包括介绍文档, Verilog源码, 在Quartus II 8.1环境下测试通过-FPGA development board SRAM VerilogHDL prepared to read and write test procedures, including the descr iption document, Verilog source code, the Quartus II 8.1 environment te
DE2_pong_demo
- de2,altera fpga开发板，自带的源码，pong_demo-de2, altera fpga development board, comes with source code, pong_demo
TX
- 1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
music_ok
- 简单的通过FPGA控制蜂鸣器播放音乐程序（verilog 源码）-Through the FPGA to control the buzzer play the music program (Verilog source code)
FPGA_atel2_bin
- 用FPGA和单片机实现的串口设计，有源码-FPGA and MCU serial design, source
pro002_keyboard
- 键盘鼠标的源码及约束（verilog）已用FPGA实现-Keyboard and mouse the source and constraints [verilog] has spent FPGA realize
sopc_led
- 基于EP3C25写的利用FPGA和SOPC做流水灯的Verilog源码-EP3C25 written based on the use of FPGA and SOPC do Verilog source water lights
ENCODE
- 本源码实现交织编码，源码为VHDL语言。运行于发射端FPGA。-Interleaved Coded achieve this source, source code for VHDL language. Running on the transmitter FPGA.
risc
- RISC（reduced instruction setcomputer，精简指令集计算机）是一种执行较少类型计算机指令的微处理器。改源码是vhdl语言，能在FPGA上跑。-RISC [reduced instruction setcomputer, Reduced Instruction Set Computer] is an implementation of fewer types of computer instructions to the microprocessor. VHDL s
hdl
- 网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。-a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong. tested.
Example-b3-1
- ALTER FPGA/GPLD设计（初级篇）的源码，只是其中的一部分供大家参考，如果还有用到其他的，请联系我-ALTER FPGA/GPLD design (primary chapter) of the source, is only one part of it for public consultation, if there are other uses, please contact me