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Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
I2C
- 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
I2C-Master-_-Slave-Core
- 用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
I2C
- 基于FPGA的I2C总线主控器的设计与实现-Based on the I2C bus master FPGA Design and Implementation
wishbone_i2c_master_vhd
- wishbone i2c master vhdl code
I2C
- I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This mo
i2c_master_slave_core
- I2C master/slave IP core
VHDL_i2cs_CPLD
- 占用寄存器超少的,I2C从模式的代码的VHDL源代码,很有用哦!-Occupation register ultra-small, I2C slave mode code VHDL source code, useful Oh!
i2c_master
- 测试i2c总线的主机代码，可以测试从机的功能，很方便使用-verilog cold i2c master
I2C_code
- 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
i2c
- I2C verilog代码，支持master和slave方式，内置CPU接口-I2C verilog RTL code， support master and slave mode
module-i2c
- I2C MASTER CODE FOR VERILOG AND FGPA IMPLEMENTATION.I WILL SUPPLY FULL CODE IF NE-I2C MASTER CODE FOR VERILOG AND FGPA IMPLEMENTATION.I WILL SUPPLY FULL CODE IF NEEDED
I2C-master-Architecture.v1.1
- Architechture for I2C master to design the VHDL code
i2c-master
- I2C Master Code in Verilog using Finite State Machine.
i2c-master
- i2c 总线 host 控制器 ， fpga上验证过，可以实现i2c 通信。-verilog IP for i2c master controller
an i2c master controller
- an i2c master controller written in vhdl
I2C-Master
- I2C Master for Metis to setup MCP4661
I2C
- i2c master，支持多种波特率，支持arbitration。(I2C master, support a variety of baud rates, support arbitration.)
i2c_master_ip_for_nios
- i2c master ip for altera nios, add in qsys