搜索资源列表
i2c_Verilog
- Verilog开发的I2c接口模块，如何需要更详细的资料，请参考www.opencores.org网站-Verilog development I2C interface module, how the need for more detailed information, please refer to website www.opencores.org
S12_AudioLoopback_DAV_MIC
- 从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code
spi_interface
- 介绍了如何用vhdl语言实现处理器的spi接口-Describes how to use VHDL language processor spi interface
8237
- 关于vhdl对硬件接口8237的编程，可以在进行fpga/cpld设计是作为模块用到-VHDL for the hardware interface on the 8237 programming, you can carrying out fpga/cpld design is used as a module
cpldbus51
- CPLD与8051的总线接口VHDL源码-CPLD with 8051 bus interface VHDL source
usb_funct
- VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.
VGA
- 基于FPGA嵌入式开发实现的VGA接口，已经验证通过。-FPGA-based embedded development to achieve the VGA interface, has been adopted to verify.
miniUART
- 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
jtag_uart_0
- jatag在nios环境下的接口代码，可在ISE或quartus下完成调试-Nios jatag environment in the interface code, can be accomplished under the ISE or Quartus debugging
RAM
- 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
aa
- xilinx环境下开发vhdl语言串行接口设计-Xilinx VHDL language development environment serial interface design
SimpleBehavioralSRAMModel
- HC164用来驱动数码管以及LED指示灯，动态扫描数码管的是利用视觉暂留的特性进行显 示景物引起人的视觉印象，在景物消失后还能在视网膜上保持0。1秒的时间叫做视觉暂 留。可以将数据刷新速率可以为10Hz(0.1s)，同时我们需要对四位数据进行扫描，因此 数据刷新速率最低应该为10Hz×4。最高可以为50MHz(HC164可以工作在50－175MHz)。 根据实际情况我们可以定为 762.939453125 = 50MHz因此接口处led,seg_value,dot数据的变化速率最
eth_ocm_80_2
- ethernet wishbone interface
FPGA_BT_656
- 采用FPGA通过BT_656接口实现传输4路视频流的方法 -FPGA through the use of BT_656 interface 4-way video stream transmission method
VHDLplj
- (1)设计4位十进制频率计测量范围: 1Hz～9999Hz (2）测量的数值通过4个数码管显示 (3）频率超过9999Hz时，溢出指示灯亮，可以作为扩大测量范围的接口-(1) the design of four decimal frequency measuring range: 1Hz ~ 9999Hz (2) measurement values through four digital tube display (3) the frequency of more than 999
speednew
- ISA板卡，CPLD原理图，altera maxII CPLD芯片。实现运动控制，标准安川伺服器控制接口。-ISA board, CPLD schematic, altera maxII CPLD chip. The realization of motion control, the standard control interface YASKAWA server.
i2cverilog
- 采用verilogHDL编写的I2C接口及SPI接口模块，经过测试 相当不错 COPY过去可直接使用-VerilogHDL prepared using I2C interface and SPI interface module, tested pretty good the past can be directly used COPY
uart2fli
- Modelsim FLI接口设计实例，适合学习Modelsim fli接口编程者学习。-Modelsim FLI interface design for learning Modelsim fli learn programming interface.
EG7014_v1.0
- 用于fpga对EG7014液晶屏的刷新显示。avalone接口。-For the FPGA on the EG7014 LCD display refresh. avalone interface.
s3esk_rotary_encoder_interface
- Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Ro