搜索资源列表
用vhdl语言编写的2进制到10进制转换的程序
- 本文为用vhdl语言编写的2进制到10进制转换的程序，为doc格式，使用前复制于maxplus等相应软件中使用。,This article was prepared by using VHDL language 2 hex to 10 hex conversion procedures for the doc format, the use of pre-replication in maxplus, such as the use of corresponding software.
FFT_16.rar
- FFT快速傅立叶变换-verilog，基于verilog的FFT源码，QuartusII上仿真通过,FFT Fast Fourier Transform-verilog, the FFT-based verilog source, QuartusII through the simulation
JPEG_model
- 关于JPEG接口的通信相关的程序，实现JPEG接口功能。-JPEG interface communication about related procedures, implementation JPEG interface functions.
JPEG_model
- 关于JPEG接口的通信相关的程序，实现JPEG接口功能。-JPEG interface communication about related procedures, implementation JPEG interface functions.
Mars_EP1C6F_Fundermental_demo(Verilog)
- FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
project4Xilinx
- vga code for xilinx
pictureviewer
- picture_viewer图片浏览器,可在LCD上显示存储在SD卡根目录:/image目录下的JPEG图片，图片格式只允许是JPEG，图片大小可以任意，如果超过800*480图片解码可能会比较慢。-picture_viewer
Jpeg_encode
- A very good project and very complex. It was written for a bachelor thesis. It does the hardware acceleration to compress an image(jpeg)
MSP430C
- 用FPGA实现JPEG的Verilog源代码-JPEG with the FPGA implementation of the Verilog source code
jpeg_verilog
- Jpeg压缩的Verilog代码，小图片-Jpeg compression of the Verilog code
datacompresstion12
- jpeg velrilog code its a very good project for mainproject
Designfiles
- deals about video compression technique jpeg format JPED_enc
buffer_comp.vhd
- Describe the TABLE FOR ENCODER TO DESIGN jpeg -Describe the TABLE FOR ENCODER TO DESIGN jpeg
q_rom.xcp
- dESIGN THE ROM ENCODER FOR jpeg
FPGA_JPEG_discode
- FPGA设计的JPG解码器的设计经典，是JPG解码器设计的指导与方法技术的全面的资料-JPG decoder FPGA design design classics, is the JPG decoder design guidance and comprehensive information on methods and techniques
JPEG_WEBINAR
- JPEG DCT C 代码，可在Catapult下生成VHDL -JPEG DCT C code for VHDL generation in Catapult
djpeg
- JPEG解码的Verilog源码，适合于了解JPEG的算法。-JPEG decoding of Verilog source code, for understanding the JPEG algorithm.
jpeg_ashu.tar
- its is jpeg interface in vhdl
81
- 一个关于ＪＰＥＧ的例子，是用Verilog编写的，可以综合。-A case of JPEG is written in Verilog, can be integrated.
Project12112011
- Program for Code Gerneration