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I2C
- 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language:
opencores_i2c
- I2C 总线协议通过两线串行数据SDA 和串行时钟SCL 线在连接到总线的器件间传递信息,每个器件都有一个唯一的地址识别,而且都可以作为一个发送器或接收器.-Through the two-wire I2C serial bus protocol data SDA and serial clock SCL line is connected to the bus transfer information between devices, each device has a unique addr
I2C_vhdl
- IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects whic
i2c
- I2C 通信模块 scl - I2C时钟信号 -- * sda - I2C数据信号 -- * ok - I2C读/写完成 -- * ack - 输入写操作的数据到本模块后，得到本模块的确认 -- * ntf - 读操作完成后，通知外部数据已好 -- * dat_o - 读操作结束后输出的数据-I2C communication module scl- I2C clock signal-* sda is- I2C data signal-* o
i2cBUS
- Altera的I2C总线FPGA程序，内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source
I2C_MUX
- I2C multiplexer.This module implements the logic for Multiplexing SDA and SCL lines of MCU to connect it to one of the SFP Ports-I2C multiplexer.This module implements the logic for Multiplexing SDA and SCL lines of MCU to connect it to one of