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sha-1.rar
- 本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。,The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
SHA_1_V
- 基于FIPS 180-4标准的SHA-1算法的verilog HDL实现-FIPS 180-4 standard SHA-1 algorithm-based verilog HDL implementation
SHA-256
- 基于FIPS 180-4标准的SHA-256算法的verilog HDL实现-SHA-256 algorithm based on FIPS 180-4 standard verilog HDL implementation
sha1_v01
- 基于FIPS 180-4标准的SHA-1算法的verilog HDL实现，分模块分别实现-FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve
sha1-progect
- Xilinx XC2VP20 FPGAs. The complete SHA-1 chip Verilog source
sha1
- 利用verilog语言实现了SHA-1机密算法，具体算法与加密芯片ds28e01一致。-Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.
DS28E01_final
- 基于SHA-1算法和DS28E01加密芯片的FPGA系统设计，该上传文件为整个设计的系统文件。Quarter软件编程的Verilog程序，包含仿真调试界面。-Design of FPGA system based on SHA-1 algorithm and DS28E01 encryption chip。
ARS_SHA_1
- sha-1主控制模块实现了对整个sha-1流程的控制(The SHA-1 main control module realizes the control of the whole SHA-1 process.)